TSMC, the world’s leading foundry, held its shareholders’ meeting on June 4th. This marked the last shareholders’ meeting chaired by TSMC Chairman Mark Liu.

According to a report from Commercial Times, with the conclusion of the era of TSMC’s dual leadership, the baton will be passed to President C.C. Wei to lead TSMC forward. During Liu’s final shareholders’ meeting, Liu further discussed TSMC’s future development plans.

• Discussing Operational Growth: Mark Liu Foresees a Year of Significant Expansion

Liu views the demand for AI optimistically, believing that this year will be one of significant growth for TSMC. He indicates that although last year had a lower base, the ongoing surge in global AI and server deployments continues to drive demand for advanced semiconductors in the market. Consequently, he holds deep confidence in TSMC’s future growth.

Meanwhile, Liu also emphasized that they are accelerating investment and future development, particularly in addressing the insatiable demand for AI computing power. Liu then highlighted their approach to tackling challenges head-on, noting that this ongoing process of learning and overcoming obstacles has fostered high levels of trust from their customers.

Additionally, when asked about the possibility of increasing capital expenditure to meet AI demand leading to a slowdown in dividend growth, Liu responded that TSMC’s growth and capital expenditure for the next five years will be continuously reviewed on a monthly basis.

CFO Wendell Huang elaborated further on whether capital expenditure affects dividend distribution, stating that TSMC plans capacity based on long-term demand and is not influenced by short-term economic fluctuations. After deducting capital expenditure, 70% of free cash flow will be allocated for dividend distribution, thus cash dividends are expected to increase gradually.

Regarding the issue of water and power shortages in Taiwan, Mark Liu mentioned that TSMC’s electricity consumption accounts for 8% of Taiwan’s total electricity usage this year and is expected to reach around 11-12% by 2030.

• Strengthening Fab Intelligence: C.C. Wei Stresses TSMC’s Continued Advantage

TSMC President C.C. Wei remarked that 2023 posed significant challenges for the global semiconductor industry. He noted that while the world economy was recovering from over two years of the pandemic, overall, it remained relatively sluggish. Factors such as persistent high inflation and interest rates also impacted the semiconductor industry’s inventory adjustment cycle.

Still, C.C. Wei highlighted that despite challenges, TSMC’s technological edge propelled the company to outperform the semiconductor manufacturing industry in 2023. This advantageous positions them well to capitalize on future growth opportunities in AI and High-Performance Computing.

Wei also underscored TSMC’s pivotal role as a driving force behind the rise of generative AI-related applications last year. He believes that AI models require more powerful semiconductor hardware support, which necessitates the use of the most advanced semiconductor manufacturing process technology.

Additionally, Wei highlighted TSMC’s achievements in 2023. These achievements include shipping 12 million equivalent wafers of 12-inch diameter, with sales from advanced process technologies (7 nanometers and below) accounting for 58% of total wafer sales, a 5% increase from the previous year. Furthermore, TSMC offers 288 different process technologies, producing nearly 12,000 different products for 528 customers.

• C.C. Wei Asserts TSMC’s Dominance

Amidst competitors’ pursuit, Mark Liu emphasizes TSMC’s serious consideration of every competitor, as there will always be competitors regardless of who they are. Currently, TSMC maintains a technological lead, focusing on whether TSMC’s pace of progress surpasses that of its competitors. TSMC aims to progress faster than others and believes it’s unlikely to be overtaken.

C.C. Wei also mentioned that AI applications are vast and in their early stages. Due to TSMC’s technological leadership, the company is in a highly advantageous position and currently faces no competitors.

On the potential expansion of capital expenditure, Wei states that TSMC will proceed with utmost caution and vigilance. The investment strategy in the upcoming years will remain unchanged, meticulously considering capital expenditure plans and capacity planning based on market demand. Whether it will exceed the previous USD 100 billion over three years remains to be seen.

Regarding the cost of setting up plants in the U.S. and issues related to the U.S. presidential election, Mark Liu stated that although establishing plants in the U.S. is expensive, TSMC manages to keep costs lower than its competitors.

He further noted that the fragmentation of production bases is an global trend, with most Taiwanese companies moving in this direction.

When asked whether customers are demanding the relocation of products or production to the U.S. or other regions, C.C. Wei acknowledged that the instability between China and Taiwan is a concern for the supply chain.

While the issue has been discussed, he emphasized that relocating all production from Taiwan, which accounts for about 80-90% of TSMC’s capacity, is “impossible.” TSMC hopes for no conflict between the two sides, as it would raise concerns far beyond the semiconductor industry.

Read more

• [News] Fueled by AI Demand, TSMC Targets its System-on-Wafer Manufactured with CoWoS to Enter Mass Production in 2027
• [News] Four Semiconductor Applicants for Taiwan’s Chip Act Tax Incentives – TSMC and MediaTek Expected to Benefit

(Photo credit: TSMC)

The 2024 Computex Taipei has kicked off, with NVIDIA CEO Jensen Huang delivering a speech on the industry’s prospects and future amidst the AI wave. According to a report from Commercial Times, during a media interview on the evening of June 3, Huang revealed plans for NVIDIA to establish an R&D center in Taiwan within the next five years.

Jensen Huang pointed out that NVIDIA already has a great AI research team. He confirmed the importance of Taiwanese partners, stating that TSMC is very important to NVIDIA’s operations, as well as expressing gratitude to partners such as Foxconn, Quanta, and ASUS for their support.

Huang further mentioned that within the next five years, NVIDIA will set up a large design center in Taiwan, indicating that the GPU giant is looking for a very spacious location and will hire at least 1,000 engineers.

When asked by the media about the speculation regarding his meeting with AMD CEO Lisa Su, Huang revealed that he did not attend her speech but acknowledged that AMD is a great company. He mentioned that he doesn’t expect to meet Su but didn’t rule it out the possiblity completely, adding that if it happens, he would welcome it.

Read more

• [News] A Recap of NVIDIA’s Four Major Application Areas of New Technology from Jensen Huang
• [News] AMD Unveils MI325, Claiming 30% Faster Computing Power than NVIDIA’s H200

(Photo credit: AMD)

The application period for the tax incentives under Taiwan’s Chip Act ended in late May. According to a report from the Economic Daily News, the Ministry of Economic Affairs announced on June 3rd that four semiconductor-related companies have applied, with the review process expected to be completed by mid to late July. Reportedly, it is said that major semiconductor companies, such as TSMC and MediaTek, have submitted their applications.

Under this act, eligible companies can benefit from certain tax deduction measures, including a 25% tax deduction for expenses on cutting-edge innovative R&D expenses and a 5% deduction on expenses of advanced process equipment, reportedly to be the most generous tax deduction measures ever in Taiwan.

The first round of applications from enterprises was accepted in February of this year, with the deadline on May 31st.

Regarding the eligibility criteria, according to the investment deduction measures announced by the Ministry of Economic Affairs, an eligibility company’s R&D expenses must reach NTD 6 billion, while its R&D intensity be at least 6%, and expenditures on equipment for advanced processes must reach NTD 10 billion.

The aforementioned criteria are not restricted by industry category. However, an effective tax rate of 12% for 2023 is required to qualify for the tax reductions under Article 10-2 of the Statute for Industrial Innovation.

Per the same report, it is understood that in 2023, there are nine listed companies meeting the two major thresholds, namely, reaching the NTD 6 billion threshold for R&D expenses and an R&D intensity of 6%, of which TSMC and MediaTek may potentially benefit from.

The Industrial Development Bureau stated that only four companies have applied for the tax benefits under the Taiwan Chip Act. They did not disclose the names of these companies, only mentioning that all applicants are semiconductor-related firms. It is widely anticipated that TSMC and MediaTek, the two most competitive companies in the country with the highest investment in R&D, are likely to benefit from the Taiwan Chip Act.

Read more

• [News] Taiwan’s Chip Act Takes Effect in February, TSMC to Benefit from Historic Tax Incentives

(Photo credit: TSMC)

On May 31, STMicroelectronics announced to build a new high-volume 200mm silicon carbide (SiC) facility in Catania, Italy, for power devices and modules as well as test and packaging.

According to a report from WeChat account DRAMeXchange, the new plant aims to commence production in 2026 and ramp to full capacity by 2033, with a full production capacity of up to 15,000 wafers per week. The total investment is expected to be around EUR 5 billion, with a support of around EUR 2 billion provided by the State of Italy in the framework of the EU Chips Act.

ST stated that Catania Silicon Carbide Campus will serve as the central hub of ST’ s global SiC ecosystem, integrating all steps in the production flow, including SiC substrate development, epitaxial growth processes, 200mm front-end wafer fabrication and module back-end assembly, as well as process R&D, product design, advanced R&D labs for dies, power systems and modules, and full packaging capabilities. This will achieve a first of a kind in Europe for the mass production of 200mm SiC wafers.

Currently, ST is producing its flagship high-volume SiC products on two 150mm wafer production lines in Catania, Italy, and Ang Mo Kio, Singapore. The third center is a joint venture between ST and San’an, which is now building a 200mm plant in Chongqing, China, dedicated to serving ST’s Chinese customers.

ST’s wafer production facilities are supported by automotive-qualified, high-volume assembly and test operations in Bouskoura (Morocco) and Shenzhen (China). SiC substrate R&D and industrialization is undertaken in Norrköping (Sweden) and Catania, where ST’s SiC substrates manufacturing facility is ramping up production and most of ST’s SiC product R&D and design staff are based.

SiC is a compound semiconductor material with inherent properties that offer superior performance and efficiency in power applications compared to silicon. Driven by market demands in new energy vehicles, photovoltaic storage applications, the usage volume of SiC power devices continues to rise.

As per TrendForce’s survey, the market size of global SiC Power Device was around USD 3.04 billion in 2023 and is expected to grow to USD 9.17 billion by 2028 at a CAGR of 25%.

Read more

• [News] A Price War in SiC Wafer Sector seems to Start
• [News] Continuous Breakthroughs in SiC Substrates, Global 8-Inch Fab to Reach 11

(Photo credit: STMicroelectronics )

At TSMC’s 2024 Technology Symposium in late May, Kevin Zhang, TSMC Senior Vice President of Business Development, has shared the company’s latest development on advanced packaging. This article recaps the highlights in the forum, featuring TSMC’s breakthroughs regarding advanced packaging.

Advanced Packaging

SoW (System-on-Wafer Integration Technology)

SoW adopts TSMC’s InFO and CoWoS packaging technologies to integrate logic dies and HBM memory on the wafer. By doing so, TSMC aims to enhance performance and speed not just at the chip level, but the system level as well.

Currently, TSMC’s system-on-wafer manufactured with InFO technology has entered mass production. Afterwards, the company plans to develop and launch SOW using CoWoS technology to integrate SoC or SoIC, HBM, and other components together.

TSMC eyes its System-on-Wafer manufactured with the CoWoS technology to enter mass production in 2027, while its target applications would include AI and HPC, expanding the computational power needed for data centers of the next generation.

3DFabric

TSMC’s 3DFabric technology family includes three major platforms: SoIC, CoWoS, and InFO, encompassing both 2D and 3D front-end and back-end interconnect technologies.

SoIC

The SoIC platform offers two stacking solutions: SoIC-P (Bumped) and SoIC-X (Bumpless). The first solution, SoIC-P, is a micro-bump stacking solution suitable for cost-effective applications such as mobile devices.

The other solution, SoIC-X, adopts Hybrid Bonding, which is ideal for HPC and AI demands. The advantage of this solution is that the pitch between contacts can be reduced to a few micrometers (µm), increasing the interconnect interface between two chips while achieving a new level of interconnect density.

TSMC’s current bond pitch density with Hybrid Bonding has been reduced to 6 micrometers, and it aims to further reduce it 2 to 3 micrometers. In the meantime, the company has been advancing micro-bump technology, currently at over 30 micrometers, with the future goal of reducing it to the teens.

TSMC revealed that customer demand for SoIC-X technology has been increasing, with 30 customer design tape-outs expected by the end of 2026.

CoWoS / InFO

The CoWoS advanced packaging family includes three members: CoWoS-S, CoWoS-L, and CoWoS-R. The three platforms can mainly be differentiated by their intermediate layer materials, which may also affect the cost. In other words, CoWoS-S utilizes silicon interposer, CoWoS-L uses LSI (Local Silicon Interconnect), while CoWoS-R uses RDL (Redistribution Layer) wiring to connect small chips.

Depending on product requirements, SoIC chips can be integrated with either CoWoS or InFO. AMD’s MI300A / MI300 X is the first product to adopt SoIC-X and CoWoS technology.

One of the most well-known product which adopts TSMC’s CoWoS-L technology would be NVIDIA’s Blackwell AI accelerator, which integrates two SoCs using 5nm with eight HBM into one module.

Moreover, TSMC’s CoWoS technology integrates advanced SoCs/SoICs with HBM to meet the requirements of AI chips. Its SoIC has entered mass production through the CoWoS-S platform. Going forward, TSMC plans to develop a SoIC chip with an eight-time mask size (using the A16 process) and a CoWoS solution with 12 HBM stacks. This updated version is expected to enter mass production in 2027.

(Photo credit: TSMC)