Recently, IC design company Marvell announced an expansion of its long-term partnership with TSMC to include 2-nanometer technology. They will collaborate on developing the industry’s first 2-nanometer semiconductor production platform optimized for accelerating infrastructure.

Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and  Rapidus.

• Marvell

According to Marvell’s press release, it has stated that Marvell has transitioned from a follower to a leader in integrating advanced node technology into silicon infrastructure.

Marvell first bringing advanced node technology to infrastructure silicon with its 5nm platform, followed by the release of several 5-nanometer designs and the profolio of the first silicon infrastructure product lineup based on TSMC’s 3-nanometer process.

“Tomorrow’s artificial intelligence workloads will require significant and substantial gains in performance, power, area, and transistor density. The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI,” said Sandeep Bharathi, chief development officer at Marvell.

• TSMC

TSMC commenced mass production of its 3-nanometer process in 2022, with profitability realized starting from the third quarter of 2023. By the fourth quarter of 2023, the 3-nanometer process contributed to 15% of wafer revenue, and its revenue share has been steadily increasing.

According to TrendForce, the foundry market is expected to grow by 7% in 2024, largely attributed to TSMC’s ramp-up of its 3-nanometer process. This has further increased TSMC’s market share.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures. It is anticipated that N2 will commence mass production in 2025, leading the industry in terms of density and energy efficiency.

The N2 backside power delivery solution is slated for release in the latter half of 2025 and is expected to enter mass production in 2026, primarily targeting the High-Performance Computing (HPC) sector.

Furthermore, due to the current high demand for 2-nanometer processes from all AI innovators worldwide surpassing that for 3-nanometer processes, almost all AI innovators are collaborating with TSMC on 2-nanometer process technology. The main applications are primarily focused on high-performance computing (HPC) and smartphones.

Consequently, TSMC has announced plans to expand its production capacity for 2-nanometer processes. Originally, two 2-nanometer fabs were planned for the Kaohsiung facility, but now consideration is being given to constructing a third 2-nanometer fab.

• Samsung

Samsung commenced mass production of its 3-nanometer process in June 2022. According to the latest industry reports, Samsung has developed a “second-generation 3-nanometer” process, renamed as “2-nanometer”, with plans for mass production before the end of this year.

At the 2023 Samsung Foundry Forum, Samsung Electronics unveiled the latest roadmap for its 2-nanometer process. Samsung Electronics President and Head of Foundry Business, Siyoung Choi, disclosed that Samsung will first mass-produce 2-nanometer chips for mobile terminals starting from 2025. Subsequently, in 2026, the technology will be applied to high-performance computing (HPC) products, followed by expansion to automotive chips by 2027.

Unlike TSMC, which opted for Gate-All-Around (GAA) structure at the outset of its 2-nanometer process, Samsung has been utilizing GAA structure since its 3-nanometer process. This suggests that Samsung may have more experience in new structures compared to TSMC, thus giving Samsung an advantage in its 2-nanometer node.

In the past, when Samsung Electronics transitioned from 7-nanometer to 5-nanometer process technology in 2020, the second generation 7-nanometer process technology was renamed as 5-nanometer process technology.

Samsung Electronics’ 7-nanometer process technology became the world’s first to use Extreme Ultraviolet (EUV) lithography in 2019, making it more stable and enabling the company to further shrink transistor sizes. This was also the reason for renaming the second generation 7-nanometer process to 5-nanometer process at that time.

A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

It is reported that PFN has been collaborating with TSMC since 2016, but this year, it has decided to produce the next generation of AI chips at Samsung’s 2-nanometer node. According to the agreement, Samsung will utilize its latest 2-nanometer chip fab technology to manufacture AI accelerators and other AI chips for PFN.

• Intel

As per Intel’s previously announced plans, the company aims to catch up with and surpass TSMC by 2024 or 2025. At this year’s “Direct Connect” conference hosted by Intel Foundry Services, the company unveiled its latest technological roadmap.

Intel has reported that its primary product, Clearwater Forest, which is under the 18A process, has been completed and is set for production in 2025. Intel’s 18A process is often compared with TSMC’s N2 (2-nanometer) and N3P (3-nanometer) processes in terms of performance, with each company advocating for its own advantages.

Intel CEO Pat Gelsinger emphasizes that both 18A and N2 utilize GAA transistors (RibbonFET), but the 1.8-nanometer node will adopt BSPND, a backside power delivery technology that optimizes power and clock. TSMC, on the other hand, believes that its N3P (3-nanometer) technology will rival Intel’s 18A in power consumption, performance, and area (PPA), while its N2 (2-nanometer) will surpass it in all aspects.

Additionally, Intel’s 20A manufacturing technology is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and backside power delivery network (BSPDN). These aim to achieve higher performance, lower power consumption, and increased transistor density.

Meanwhile, Intel’s 18A production node aims to further refine the innovations of 20A and provide additional PPA improvements from late 2024 to early 2025. Per Intel’s statements regarding its fab processes, its 2-nanometer technology is expected to be the earliest to debut.

Of particular note, Intel announced for the first time at the conference the development of 14A (1.4nm) and its evolutionary version, 14A-E. Intel’s 14A process is the industry’s first node to utilize ASML High-NA EUV lithography tools, making Intel the first company in the industry to acquire cutting-edge High-NA tools. Intel expects to develop 14A by 2027.

• Rapidus

In addition to the aforementioned semiconductor foundries, a Japanese company, Rapidus, is worth noting as well. Established in August 2022, Rapidus was jointly founded by eight Japanese companies including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash giant Kioxia, and Mitsubishi UFJ.

On January 22nd of 2024, Rapidus President Junichi Koike announced during a press conference that construction of the Rapidus 2-nanometer chip fab in Japan is progressing smoothly, and the trial production line is scheduled to commence operations in April 2025 as planned. Additionally, there are plans for the construction of a second and third facility in the future.

In September of last year, Rapidus began construction of Japan’s first logic chip fab, “IIM-1,” in Chitose City, Hokkaido, capable of producing chips below 2 nanometers. It is reported that the fab is expected to be completed by December of this year.

Previously, Rapidus signed a collaboration agreement with IBM to develop technology based on IBM’s 2-nanometer process. IBM had already introduced the world’s first 2-nanometer process chip back in 2021. Similarly, IBM’s 2-nanometer process also utilizes GAA (Gate-All-Around) structure. This partnership provides Rapidus with the technical support necessary for advanced process development.

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• [News]The 2nm Semiconductor Foundry Race Between TSMC, Samsung, Rapidus Begins with an Equipment Battle

(Photo credit: TSMC)

Taiwan’s residential and industrial electricity prices have long ranked among the lowest globally, but, as per CNA’s report, to stabilize Taiwan Power Company’s finances, electricity price hikes in April are nearly finalized. Among these adjustments, industrial electricity rates will vary based on the specific industry’s consumption patterns.

Under the current plan, residential and general industrial electricity will be categorized into three tiers, each subject to different price adjustments. As for the “super consumers” in the high-voltage category (defined as those with over 5 billion kilowatt-hours consumed annually for two consecutive years), the rate hike could reach up to 30 percent, impacting major consumers in the semiconductor firms like TSMC and Micron.

As per the report from Taiwanese media NowNews, market concerns are mounting over the 24-hour operations of semiconductor fabs. Despite the potential for energy savings through “time-based electricity pricing,” the effectiveness of such measures may be limited. This could significantly escalate operating costs for companies.

Regarding the potential impact of electricity price adjustments on the semiconductor industry, Taiwanese Minister of Economic Affairs Mei-Hua Wang recently stated that even with 24-hour electricity usage, TSMC maintains high energy efficiency. Moreover, semiconductor fabs primarily export their products after manufacturing. Compared to fabs in other countries, Taiwan’s electricity prices are still relatively low.

The definition of high-voltage super consumers entails annual electricity usage exceeding 5 billion kilowatt-hours, with consecutive growth over two years. Different companies will be distinguished within this category. Semiconductor manufacturers, as well as data centers, will be included in the high-voltage super consumer classification.

However, the rate hike of electricity prices for these significant consumers will depend on the subsidy budget allocated by the Executive Yuan. If a subsidy of TWD 100 billion (roughly USD 3.2 billion)  is allocated, the rate hike could exceed 30%. Even with a subsidy of TWD 150 billion (roughly USD 4.8 billion) , the increase would still surpass 20%.

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• [News] TSMC to Expand Production with New Facilities Across Taiwan in April

(Photo credit: TSMC)

China is reportedly in the process of establishing its third-phase of its big fund, with plans to inject USD 27 billion in funding aimed at supporting top-tier technology development, as per Bloomberg’s report. The goal is said to be enhancing China’s semiconductor self-sufficiency and overcoming export restriction measures imposed by the United States.

According to Bloomberg, the funding for the third phase of Big Fund primarily originates from local governments, state-owned enterprises, and their investment branches, with relatively smaller contributions from the central government. This aligns with China’s strategic focus on concentrating resources to support the development of key technologies.

The initial round of financing for the third phase of Big Fund aims to raise USD 27 billion, which, in the context of China’s semiconductor industry standards, is a relatively modest amount. The fund will directly support local companies and finance three to four sub-funds, diversifying transaction sources and investment strategies.

The National Integrated Circuit Industry Investment Fund, commonly referred to as the “Big Fund,” originated from the Chinese State Council’s “Outline for the Promotion of National Integrated Circuit Industry Development” issued in June 2014. Its ultimate goal is to bring China’s semiconductor industry up to international standards by 2030 and nurture a group of companies to become international Tier 1 suppliers.

As early as September of 2023, the second phase of the Big Fund initiated a round of financing, raising USD 41 billion to support local fab equipment manufacturers. As for the third phase of the Big Fund, this USD 27 billion will be allocated to critical projects across various regions in China.

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• [News] US Government Considers Adding ChangXin Memory Technologies to Entity List, Imposing Further Sanctions on Chinese Firms
• [News] Big Fund II Infuses HLMC with an Additional USD 1 Billion, Potentially Eyeing on More Advanced Processes

(Photo credit: iStock)

According to sources cited in Bloomberg’s report, the US government is considering imposing sanctions on Chinese technology firms, including ChangXin Memory Technologies (CXMT), in its latest move against China’s advanced semiconductor sector.

The same report has pointed out that the US Department of Commerce’s Bureau of Industry and Security (BIS) is currently considering including CXMT in the Entity List, which would restrict the listed companies’ access to US technology. Apart from CXMT, US officials are also contemplating restrictions on five other Chinese companies, though the final list has yet to be confirmed.

Regarding this matter, the BIS and White House National Security Council declined to comment.

CXMT is a major Chinese DRAM manufacturer whose products include chips applicable in computer servers, smart vehicles, and other devices. Its primary competitors include Micron, Samsung Electronics, and SK Hynix. Micron.

The recent actions by the US government reportedly stem from Huawei’s breakthrough last year in circumventing US restrictions to acquire advanced process chips, specifically obtaining chips using the 7-nanometer process from SMIC (Semiconductor Manufacturing International Corporation). This allowed Huawei to make a comeback in the 5G smartphone market, prompting concerns and responses from the US government.

Gina Raimondo, the US Secretary of Commerce, has responded by stating that the US will take “as strong and effective action as possible” to uphold national security interests.

Currently, companies that have been listed on the Entity List by the US Department of Commerce include Huawei, SMIC (Semiconductor Manufacturing International Corporation), and Shanghai Micro Electronics. Additionally, China’s other major memory manufacturer, Yangtze Memory Technology Corp, was added to this restriction list in 2022.

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• [News] Bypassing U.S. Restrictions? CXMT Showcases GAA Technology for 3nm Chips
• DRAM Industry Sees Nearly 30% Revenue Growth in 4Q23 Due to Rising Prices and Volume, Says TrendForce

(Photo credit: CXMT)

As per Chinese media mydrivers’ report, it has indicated that NVIDIA updated the EULA terms in the CUDA 11.6 installer, explicitly prohibiting third-party GPU companies from seamlessly integrating CUDA software. This move has reportedly stirred up discussions among the market.

NVIDIA updated the EULA agreement for CUDA 11.6, explicitly stating, “You may not reverse engineer, decompile or disassemble any portion of the output generated using SDK elements for the purpose of translating such output artifacts to target a non-NVIDIA platform.”

This move is reportedly speculated to target third-party projects like ZLUDA, involving Intel and AMD, as well as compatibility solutions from Chinese firms like Denglin Technology and MetaX Technology.

In response, MooreThreads issued an official statement, confirming that its MUSA and MUSIFY technologies remain unaffected. MUSA and MUSIFY are not subject to NVIDIA EULA terms, ensuring developers can use them with confidence.

In fact, since 2021, NVIDIA has prohibited other hardware platforms from running CUDA software analog layers but only warned about it in the online EULA user agreement. Currently, NVIDIA has not explicitly named any parties, issuing warnings in the agreement without taking further action, although further measures cannot be ruled out in the future.

In the past, CUDA development and its ecosystem were widely regarded as NVIDIA’s moat. However, processor architect Jim Keller previously criticized CUDA on the X platform, stating, “CUDA is a swamp, not a moat,” adding, “CUDA is not beautiful. It was built by piling on one thing at a time.”

Meanwhile, according to the account rgznai100 posting on Chinese blog CSDN, NVIDIA’s actions will have a significant impact on AI chip/GPGPU companies that previously adopted CUDA-compatible solutions. NVIDIA may initially resort to legal measures, such as lawsuits, against GPGPU companies following similar paths.

Therefore, Chinese enterprises should endeavor to enhance collaboration with the open-source community to establish an open AI compilation ecosystem, reducing the risks posed by NVIDIA’s market dominance.

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• [News] HBM Manufacturers Encounter Challenges in NVIDIA Quality Tests, Raising Concerns over Yield and Production
• [News] NVIDIA Reportedly Overwhelms TSMC with 3 and 4-Nanometer Orders

(Photo credit: NVIDIA)