Following TSMC’s announcement of investing USD 20 billion to build two plants in Kumamoto, Japan, industry sources cited by a report from Commercial Times has indicated that the major global semiconductor assembly and testing provider, ASE Group, is in discussions with the Japanese government to finalize subsidies and investment details.

Reportedly, ASE plans to invest nearly NTD 10 billion (roughly USD 306.3 million) to construct its first advanced packaging plant in Kumamoto, becoming the second Taiwanese semiconductor giant to set foot in the region.

Regarding the establishment of a plant in Kumamoto, ASE Group stated that it does not comment on market rumors.

During its earnings call last week, ASE Group announced a capital expenditure increase to expand related capacities due to the upward adjustment in advanced packaging projects. This year’s capital expenditure, originally estimated at around USD 2.1 billion with a year-on-year increase of over 40%, has been raised to a potential 50% increase (up to USD 2.25 billion), potentially reaching a historic high.

The semiconductor industry is witnessing a great era of global competition with various countries pouring money into subsidies. Recently, there have been rumors of the Japanese government actively reaching out to Taiwanese semiconductor companies and offering substantial subsidies, aiming to build a complete semiconductor industry chain covering upstream, midstream, and downstream sectors.

Apart from TSMC’s decision to establish two advanced semiconductor plants in Kumamoto, Intel is also considering establishing an advanced packaging research institution in Japan, and Samsung is planning to set up advanced packaging research facilities in Yokohama.

Industry sources cited by the same report point out that these signs have indicated that after mastering wafer manufacturing technology, the next phase for Japan is to enhance the establishment of the packaging industry.

Industry rumors have recently circulated that the Japanese government has been in discussions with senior executives from ASE Group for some time, and the relevant subsidy and investment details are generally agreed upon. The location for the new facility is expected to be in Kumamoto, near TSMC’s upcoming plant. As per the same report citing sources, there is a chance that ASE’s Kumamoto facility, like TSMC’s second plant in Kumamoto, will be planned to start production before the end of 2027.

In fact, as early as 2004, ASE Group acquired full ownership of an IC packaging and testing facility in Yamagata Prefecture, Japan, from NEC for USD 80 million. However, over the past two decades, Japan’s influence in the global semiconductor sector has waned, and ASE’s acquisition of the NEC facility has not made significant operational contributions.

ASE Group’s global footprint currently includes high-end product bases in Taiwan, as well as its packaging and testing capacities in China, Japan, Malaysia, South Korea, and Singapore.

ASE is continuing its expansion efforts in Taiwan, including Kaohsiung, Zhongli, and Tanzi. Evenmore, on February 22nd, ASE Group and semiconductor giant Infineon Technologies jointly announced the finalization of an agreement. ASE Group will invest EUR 62.589 million to acquire Infineon’s backend packaging facilities located in Cavite, Philippines, and Cheonan, South Korea.

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TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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According to the report from MoneyDJ, Western Digital (WD), a well-known memory device manufacturer, reported its latest financial report after the American stock market closed on April 25. Both revenue and profit for 1Q24 were better than market expectations, mainly driven by the robust AI demand and cloud service providers’ proactive acts in AI investment, which significantly boosted data storage demand.

According to WD’s financial result for fiscal third quarter 2024 (ending March 29, 2024), revenue increased by 23% YoY to USD 3.46 billion, surpassing the expected USD 3.36 billion from LSEG’s survey. Gross margin rebounded to 29%, up 18.8 percentage points from the same period last year at 10.2%; Net profit turned from a loss to a gain of $110 million, or USD 0.34 per share, far better than the net loss of USD 580 million, or net loss of USD 1.82 per share in the same period last year. Excluding one-time expenses, adjusted earnings per share were USD 0.63.

Photo credit: WD

The main “Cloud” segment saw robust revenue growth of 29% in the third quarter to USD 1.55 billion, mainly fueled by enterprises’ acceleration and expansion of data center construction, stimulating memory demand growth, with prices also rising accordingly.

Its competitor Seagate, a HDD manufacturer, also reported impressive financial results on April 23, with last quarter’s performance beyond expectations. The company expected continued growth of AI-driven memory demand and give a positive business outlook for this quarter.

Looking ahead to fiscal fourth quarter 2024 (ending June 28, 2024), WD estimates revenue will be USD 3.6-3.8 billion; adjusted earnings per share are estimated to be USD 0.90-1.20.

WD previously announced the separation of its two main product divisions, HDD and NAND Flash. The NAND Flash division will be spun off into a new company and go public, and the transaction is expected to be completed in the second half of 2024. Moving forward, WD will focus on its core HDD business to bring greater value to shareholders.

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(Photo credit: WD)

Henri Richard, head of Rapidus Design Solutions, the US subsidiary of Japan’s semiconductor foundry startup Rapidus, and former Chief Marketing Officer at processor giant AMD, indicates that Rapidus aims to position itself as a filler of market gaps during the interview with global media The Register.

Rapidus Design Solutions, established by Rapidus in this month, is expected to bolster ties with US semiconductor design companies and wafer manufacturing technology providers like IBM. Henri Richard reportedly notes that the AI boom is boosting the advanced semiconductor foundry market, albeit with understated demand and ongoing capacity constraints. Thus, in this market trend, he asserts that even if these technologies don’t necessarily confer a competitive edge, the limitations in capacity alone should suffice to ensure Rapidus’ success.

Established in August 2022, Rapidus was jointly founded by eight Japanese companies, including Toyota, Sony, NTT, NEC, Softbank, Denso, Kioxia (formerly Toshiba Memory Corporation), and Mitsubishi UFJ, who invested collectively in its establishment. As per Rapidus’ plan, they aim to commence mass production of 2-nanometer process technology in 2027, significantly lagging behind major global players like TSMC, Intel, and Samsung.

TSMC and Samsung previously planned to mass-produce 2nm chips in 2025, while Intel is anticipated to be the first to achieve commercialization of 2nm chips. Industry sources cited by the The Register’s report also view this timing as unfavorable for Rapidus.

However, Henri Richard believes that the semiconductor process technology has reached a turning point. Assessing the success of suppliers solely based on production timelines is narrow-minded; competitiveness stems from various factors beyond production schedules.

Based on these factors, Rapidus positions itself as a fill-in player in the advanced manufacturing market, targeting small AI chip design companies as its primary market. While competitors focus on serving large clients, Rapidus aims to win over these smaller clients by offering comprehensive support services. By serving numerous small chip design companies, Rapidus can better understand the specific needs of AI chip users, rather than insisting on the latest process technology for all chips.

Henri Richard emphasizes that Rapidus itself has limited scale and cannot initially serve too many clients simultaneously. It is expected that Rapidus’s initial client base will not exceed 6 companies, allowing them to accumulate experience and capabilities.

Although there are geopolitical issues currently, establishing facilities in the US is not on Rapidus’s immediate agenda. Meanwhile, Japan represents a relatively favorable geographic location for Rapidus, offering clients a risk-diversification option.

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(Photo credit: Rapidus)

Following the recent launch of the Arm-based PC platform processor Snapdragon X Elite, which received high market acclaim, Qualcomm is reportedly doubling down by venturing into server processors. This expansion is expected to further intensify the competition amid traditional server processor giants Intel and AMD.

According to a report from the global tech media Android Authority, following the launch of the Snapdragon X Elite/Plus processors, Qualcomm is internally developing a server processor with the codename SD1, featuring their custom Oryon cores.

Reportedly, Qualcomm’s next-generation server processor will be manufactured using TSMC’s 5-nanometer process (N5P), featuring 80 Oryon cores with a maximum clock speed of 3.8GHz, 16-channel DDR5 memory with a maximum transfer rate of 5600MHz, 70 PCIe 5.0 interface links, and support for CXL v1.1. It will use a 9470-pin LGA socket and support dual-socket server configurations.

Furthermore, the status of this project is currently unconfirmed, but Qualcomm partners reportedly received briefings about it at the end of 2021 and early 2022, aligning with previous rumors. This isn’t Qualcomm’s first foray into server processors; they previously launched the Arm-based Centriq series in 2017, which was discontinued a year later.

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(Photo credit: Qualcomm)