TSMC announced during its briefing on the 18th that, due to robust demand in the 2-nanometer market, it plans to add another fab to the initially planned two fabs in Kaohsiung.

The company intends to use the 2-nanometer process for all three fabs in Kaohsiung, in addition to the originally planned 2-nanometer fab in Hsinchu’s Baoshan. Furthermore, the land recently acquired in Hsinchu Science Park will also be designated for a 2-nanometer fab. This reflects the strong preference for the 2-nanometer process among customers and underscores TSMC’s confidence in its in-house 2-nanometer process technology.

According to a report by TechNews following the briefing on the 18th, TSMC’s CFO Wendell Huang, stated in a media gathering that the strong demand in the high-performance computing and smartphone markets prompted the decision to increase the number of fabs in Kaohsiung from the originally planned two to three. Once the three 2-nanometer fabs are in full production, Kaohsiung will become a crucial manufacturing hub for TSMC’s 2-nanometer process.

In addition, with the recent approval from the Ministry of the Interior’s Urban Planning Commission, the land in Hsinchu Science Park designated for TSMC’s use, expected to be available in June 2024, is also being planned for a 2-nanometer fab.

Recent market reports suggest that TSMC, the leading semiconductor foundry, is set to proceed as scheduled with its plan to adopt the GAA (Gate-All-Around) architecture from the 2-nanometer process onward.

The P1 wafer fab in Baoshan, located in the Hsinchu Science Park, is anticipated to begin equipment installation as early as April 2024, while the Kaohsiung fab is projected to commence production using the GAA architecture for the 2-nanometer process technology in 2025.

Furthermore, in response to Intel securing the first High-NA EUV exposure equipment from ASML for its 18A advanced process, TSMC has indicated that it is also planning for High-NA EUV exposure equipment. However, the current timeline anticipates engineering verification of the High-NA EUV exposure equipment in 2024, with gradual integration into the manufacturing process set to follow.

(Image: TSMC)

TSMC Chairman Mark Liu discussed TSMC’s global expansion during earnings conference yesterday, stating that progress in the construction of TSMC’s facilities in Japan, the United States, and Germany will proceed according to the original plans. The Kumamoto facility in Japan is set to hold its opening ceremony on February 24, with mass production scheduled for the fourth quarter of this year.

According to reports from the Central News Agency, Liu mentioned that TSMC will continue to invest in Taiwan to meet the growing demand from customers. The 3-nanometer capacity will be expanded in the Tainan Science Park, with 2-nanometer production slated for 2025, based in Hsinchu and Kaohsiung. Additionally, the government has approved the expansion of the second phase of the Central Science Park, and TSMC will proceed accordingly.

He stated that the Japanese special process wafer plant will adopt 12, 16, 22, and 28-nanometer processes, with the opening ceremony scheduled for February 24 and mass production planned for the fourth quarter of 2024.

Regarding the Arizona facility in the United States, Liu mentioned that TSMC is closely cooperating with local trade and labor unions. An agreement has been signed with the Arizona Building and Construction Trades Council (AZBTC), including union training, aiming to achieve a win-win situation. The 4-nanometer process is set to begin production in the first half of 2025, providing manufacturing quality and reliability on par with Taiwan wafer plants.

As for the special process wafer plant in Germany, Liu mentioned that it will primarily address automotive and industrial needs. With support from joint venture partners, the German federal government, and local governments, construction is set to commence as scheduled in the second half of 2024.

(Image: TSMC)

TSMC reported its Q4 2023 financial results, disclosing consolidated revenue of NT$625.53 billion, net income of NT$238.71 billion, and diluted earnings per share of NT$9.21 (US$1.44 per ADR unit). The figures show a flat year-over-year performance in revenue, with a 19.3% decrease in net income and diluted EPS. However, compared to Q3 2023, Q4 demonstrated a robust 14.4% increase in revenue and a 13.1% rise in net income. All financials adhere to TIFRS on a consolidated basis.

In US dollars, Q4 revenue amounted to $19.62 billion, marking a 1.5% YoY decrease but a significant 13.6% increase from the preceding quarter. Key margins for the quarter include a gross margin of 53.0%, operating margin of 41.6%, and a net profit margin of 38.2%.

Notably, in Q4, 3-nanometer shipments constituted 15% of total wafer revenue, 5-nanometer accounted for 35%, and 7-nanometer contributed 17%. Advanced technologies, encompassing 7-nanometer and beyond, comprised 67% of total wafer revenue, highlighting TSMC’s commitment to cutting-edge semiconductor production.

Outlook for 2024: Anticipating a 6.2% Q1 Revenue Decline and Gross Margin of 52-54%; Full-Year Revenue Estimated to Grow 21% to 26%

TSMC foresees a approximately 6.2% quarter-on-quarter decline in revenue for the first quarter of 2024, with President CC Wei expressing optimism for healthy growth throughout the year. The full-year revenue growth is projected to surpass the 20% benchmark in the semiconductor foundry industry, ranging between 21% and 26%.

TSMC CFO Wendell Huang noted that the demand for high-performance computing remains robust. However, due to seasonal factors of the smartphone industry, Q1 2024 revenue is estimated to be around $18 billion to $18.8 billion, representing a 6.2% decline when calculated at the midpoint. The gross margin is anticipated to be approximately 52% to 54%, maintaining a level comparable to the fourth quarter of the previous year, while the operating profit margin is expected to be around 40% to 42%.

CC Wei stated that the semiconductor industry’s revenue, excluding memory, is expected to grow by 10% this year. Foundry industry revenue is also projected to grow by 20%. Leveraging its leading process technology, TSMC anticipates its revenue growth in 2024 to outpace the industry standard, ranging from 21% to 26%.

Regarding the 3-nanometer manufacturing process, CC Wei mentioned that mass production has commenced in the second half of 2023, contributing approximately 6% to the annual revenue. With the impetus from smartphone and high-performance computing demands, the revenue share of the 3-nanometer process is expected to increase to 15% in 2024.

Capital Expenditure: A 16% Decrease in 2023, Estimated to Fall to $28-32 Billion in 2024

TSMC disclosed a total capital expenditure of $30.45 billion for the full year of 2023, a 16.1% decrease from the $36.29 billion spent in 2022. TSMC projects capital expenditures for 2024 to range between $28 billion and $32 billion.

(Image: TSMC)

In the surge of AI advancements, a CoWoS expansion wave is rapidly underway, with TSMC showcasing ongoing ambitions in advanced packaging.

According to MoneyDJ, recent industry reports suggest that TSMC is revising upward its capacity plans for SoIC (System-on-Integrated-Chips). By the end of this year, monthly production capacity is expected to jump from around 2,000 units in late 2023 to 5,000-6,000 units, addressing robust demand in the future for AI and HPC.

TSMC’s SoIC represents an industry-first high-density 3D chip stacking technology. Through the Chip on Wafer (CoW) packaging technique, it enables heterogeneous integration of chips with different sizes, functions, and nodes. Production has commenced at its advanced backend Fab 6 in Zhunan.

Quoting industry sources, MoneyDJ reports that SoIC’s monthly capacity was initially set to expand to 3,000-4,000 units this year from 2,000 units at the end of last year. However, it is now revised upward to 5,000-6,000 units, with a goal to double the capacity by 2025.

CoWoS, a mature technology with 15 years of development, is estimated to reach a monthly capacity of 30,000-34,000 units by the end of this year. TSMC is banking on its globally dominant 3D stacking technology with SoIC. The debut of major customer AMD MI300 utilizing SoIC with CoWoS is seen as pivotal. If successful, AMD could dominate the AI server sector, making TSMC’s SoIC a significant achievement.

Furthermore, Apple, TSMC’s largest customer, is reportedly keenly interested in SoIC. It is said to adopt SoIC with Hybrid Molding technology, currently in small-scale trial production and expected to enter mass production in 2025-2026. The plan is to apply it in products like Mac and iPad, offering cost advantages over current solutions.

As for another major customer of TSMC’s advanced packaging, NVIDIA, although high-end products currently favor CoWoS packaging, the industry anticipates the future integration of SoIC technology.

(Image: TSMC)

TSMC has achieved a breakthrough in next-generation MRAM memory-related technology, collaborating with the Industrial Technology Research Institute (ITRI) to develop a spin-orbit-torque magnetic random-access memory (SOT-MRAM) array chip

This SOT-MRAM array chip showcases an innovative computing in memory architecture and boasts a power consumption of merely one percent of a spin-transfer torque magnetic random-access memory (STT-MRAM) product.

According to a report by the Economic Daily News, industry sources suggest that with the advent of the AI and 5G era, applications such as autonomous driving, precise medical diagnostics, and satellite image recognition require a new generation of memory that is faster, more stable, and has lower power consumption. MRAM, which utilizes common refined magnetic materials found in hard drives, meets the demands of this new generation of memory, attracting major players like Samsung, Intel, and TSMC to invest in research and development.

In the past, MRAM was mainly applied in automotive and base station. However, due to the characteristics of MRAM architecture, it was challenging to achieve a balance between data retention, write endurance, and write speed. A few years ago, a new architecture called Spin-Transfer Torque MRAM (STT-MRAM) emerged, addressing the aforementioned challenges and entering commercialization.

TSMC has successfully developed related MRAM product lines with 22-nanometer, 16/12-nanometer processes and secured orders in markets such as memory and automotive, seizing the MRAM business opportunity.

In a recent development, TSMC, riding on its success, collaborates with the Industrial Technology Research Institute (ITRI) to create an SOT-MRAM array chip, complemented by an innovative computing architecture.

Their collaborative efforts have resulted in a research paper on this microelectronic component, which was jointly presented at the 2023 IEEE International Electron Devices Meeting (IEDM 2023), underscoring the cutting-edge nature of their findings and their pivotal role in advancing next-generation memory technologies.

Dr. Shih-Chieh Chang, General Director of Electronic and Optoelectronic System Research Laboratories at ITRI, highlighted the collaborative achievements of both organizations.

“Following the co-authored papers presented at the Symposium on VLSI Technology and Circuits last year, we have further co-developed a SOT-MRAM unit cell,” said Chang. “This unit cell achieves simultaneous low power consumption and high-speed operation, reaching speeds as rapid as 10 nanoseconds. And its overall computing performance can be further enhanced when integrated with computing in memory circuit design. Looking ahead, this technology holds the potential for applications in high-performance computing (HPC), artificial intelligence (AI), automotive chips, and more.”

(Image: ITRI)