In addition to China, Russia has also made semiconductors one of its major focuses. According to a report by Tom’s Hardware, which cites local media CNews, the country has set aside over 240 billion rubles (USD 2.54 billion) to fund a program aimed at replacing 70% of the foreign chipmaking equipment by 2030.

This effort, according to the reports, includes the launch of 110 R&D projects to reduce reliance on imported wafer fabrication tools and eventually produce chips using 28nm-class process technology. However, it is worth noting that the total investment is 57 times smaller than what Russia plans to spend on defense in its war with Ukraine in 2025 alone, the reports note.

According to the reports, to put things in context, domestic chipmakers like Angstrem and Mikron can produce chips using mature technologies, such as 65nm and 90nm nodes. However, only 12% of the 400 tools used for chip production in the country are currently made locally.

Moreover, sanctions have worsened the situation, which raise the price of essential equipment by 40% to 50% due to the need to smuggle it into Russia, the reports indicate.

Therefore, to address these challenges, Russia’s Ministry of Industry and Trade, along with government-controlled MIET, have developed the initiative, which addresses multiple aspects of chipmaking, including manufacturing tools, raw materials, and electronic design automation (EDA) tools, according to the reports.

However, the report by Tom’s Hardware raises concerns about the feasibility of the initiative, as many of the specific details remain somewhat vague.

For instance, one of the initiative’s key goal is the development of lithography equipment for 350nm and 130nm process technologies, which has a very wide gap in between. Also, Russia intends to manufacture domestic lithography systems capable of handling 65nm and 90nm process technologies. Nevertheless, even this would represent significant progress in the country’s microelectronics production, it would still lag 25 to 28 years behind the industry’s leading edge, the report states.

Recently, Professor Xu Xiaohong and Professor Wang Fang from Shanxi Normal University, in collaboration with Researcher Xue Dingjiang from the Institute of Chemistry, Chinese Academy of Sciences, reported a template selection strategy for bottom-up synthesis of CrSbSe₃ nanoribbons.

They successfully achieved the controlled preparation of one-dimensional (1D) ferromagnetic CrSbSe₃ nanoribbons, which exhibit typical semiconductor behavior and ferromagnetism, confirming the intrinsic ferromagnetic properties of 1D CrSbSe₃ semiconductors.

With the rise of cloud computing technology, the scale and complexity of data storage have reached unprecedented levels, placing increasing demands on storage technologies. Magnetic semiconductors, as a new class of spintronic materials, hold the potential to simultaneously enable logic operations, information processing, and storage.

As a result, low-dimensional magnetic semiconductors have become an inevitable trend in the construction of nanoscale spintronic devices, aiming to minimize device size and achieve high-density integration. However, realizing such low-dimensional magnetic semiconductors remains challenging, especially for 1D ferromagnetic semiconductors with higher magnetic anisotropy, larger aspect ratios, and greater potential for nanoscale spintronic devices.

CrSbSe₃, as the only experimentally verified 1D material that possesses both ferromagnetic and semiconductor properties, is of significant importance in exploring its characteristics and applications. Until now, CrSbSe₃ nanocrystals could only be obtained through top-down exfoliation methods.

In response, the team reported a bottom-up solution method for synthesizing CrSbSe₃  nanoribbons. By comparing the formation energies of potential binary templates and ternary target products, they selected Sb2Se₃, a material with a 1D crystal structure, as the template. Half of the Sb atoms in Sb2Se₃ were replaced with Cr atoms, promoting the phase transition from Sb2Se₃ to CrSbSe₃. The synthesized CrSbSe₃ nanoribbons were approximately 5 µm in length, 80 to 120 nm in width, and about 5 nm thick. The nanoribbons exhibited soft magnetic behavior at temperatures below the Curie temperature of 71 K.

Magnetic and electrical tests conducted on individual CrSbSe₃ nanoribbons demonstrated their typical semiconductor behavior and ferromagnetism, further confirming the intrinsic ferromagnetic properties of the 1D CrSbSe₃ semiconductor. This work provides a novel bottom-up template synthesis method for ternary 1D nanoribbons, laying the foundation for the development and application of 1D ferromagnetic semiconductors.

(Photo credit: Shanxi Normal University)

The surging global demand for AI chips is straining advanced packaging capacity, driving a sharp focus on fan-out panel-level packaging (FOPLP) within Taiwan’s semiconductor industry. According to a report by Commercial Times, major packaging and testing firms such as ASE and Powertech, alongside equipment manufacturers like Gudeng, GPTC, E&R Engineering, Mirle, and analysis firm MAtek, are investing heavily in FOPLP technology.

The rapid development and expanding applications of AI chips have intensified the need for higher chip performance, smaller sizes, better heat dissipation, and lower costs. As emerging applications such as 5G, AIoT, and automotive chips continue to grow, the demand for high-performance, high-power semiconductors has surged. FOPLP technology, which enhances performance while significantly cutting costs and addressing thermal and signal integration issues, is emerging as a key trend in the market.

ASE has been working on panel-level packaging for several years. The company expects its panel-level packaging equipment to be in place by the second quarter of 2025, maintaining a technological edge. On October 2, ASE announced a nearly NT$8 billion purchase of equipment by its subsidiary, SPIL, from companies including Advantest.

Powertech has already moved into wafer-level fan-out packaging and is now shifting toward panel-level fan-out packaging. The company claims that the new technology can increase chip area output by two to three times. It has dedicated its Hsinchu plant to panel-level fan-out packaging and TSV CIS, positioning itself for future growth opportunities.

Equipment manufacturers are also seeking to capitalize on this trend. GPTC, a supplier to major foundries for InFO packaging, is expected to benefit from future FOPLP opportunities due to the similar nature of its equipment. Gudeng Precision is developing panel-level packaging transport boxes, with mass production expected in 2025.

FOPLP combined with TGV drilling is seen as the key to this technology. Analysts cited by Commercial Times highlight that FOPLP+TGV enables higher area utilization and unit capacity, which effectively reduces heterogeneous packaging costs.

E&R Engineering is focusing on drilling, testing, and cutting equipment for glass substrates, primarily supplying panel manufacturers in Taiwan and outsourced assembly and testing providers in Southeast Asia. Mirle has targeted glass substrate transport equipment, while MAtek is leading the market in glass substrate inspection technology.

(Photo credit: ASE)

The competition between Samsung and TSMC has intensified not only in securing international IC design clients but also in the field of South Korean IC design companies. According to a report by ZDNet Korea, major South Korean AI semiconductor fabless companies, which previously used Samsung’s foundry facilities, are now diversifying their manufacturing by using TSMC’s fabs for new chip mass production.

Industry sources cited by ZDNet Korea reveal that FuriosaAI initially used Samsung’s 14nm process for its first-generation chip, “Warboy,” but switched to TSMC’s 5nm process for its second-generation chip, “Renegade.” Notably, Renegade became the first chip in South Korea’s AI semiconductor sector to utilize 2.5D packaging technology with CoWoS and HBM3 memory. FuriosaAI is also planning to use TSMC’s 5nm process for its next-generation chip, “RenegadeS,” set to launch in the fourth quarter.

Similarly, DeepX, after using Samsung’s foundry process, adopted TSMC’s technology for its latest chip development this year. The company’s “DX-V3” system-on-chip (SoC) is being developed using TSMC’s 12nm process, with a target to release samples later this year. DeepX’s earlier chips, the “DX-M1” AI accelerator and “DX-H1” AI server accelerator, were produced using Samsung’s 5nm process, while the “DX-V1” AI SoC solution was made with Samsung’s 28nm process. The “DX-M1” entered mass production last month. ZDNet Korea also reports that DeepX is currently discussing with Samsung the development of next-generation chips using processes more advanced than 5nm.

Another South Korean IC design company, Moblinet, is utilizing both Samsung and TSMC’s foundry services. Its first-generation chip, “Eris,” was manufactured using Samsung’s 14nm process and began mass production in March this year. The second-generation chip, “Regulus,” is being produced using TSMC’s 12nm process and is expected to launch next year after completing testing.

ZDNet Korea also cites industry experts who emphasize that Samsung’s foundry services need to not only focus on attracting large clients but also improve services for smaller fabless companies. Similar to how TSMC grew by nurturing partnerships with small fabless firms, Samsung should bolster its process technology and develop an ecosystem for IP and fabless companies.

According to TrendForce data, TSMC maintained a global foundry market share of 62.3% in the second quarter of this year, while Samsung held an 11.5% share.

Meanwhile, in the race for major international client orders, WCCFTECH reports that Qualcomm is pursuing a dual-sourcing strategy for its Snapdragon 8 Gen 5 chip, partnering with both TSMC and Samsung. Qualcomm has previously attempted this approach, but Samsung’s inconsistent yields thwarted the plan. Qualcomm is now reportedly considering TSMC’s 3nm ‘N3P’ technology for the high-performance variant of the Snapdragon 8 Gen 5, while Samsung’s SF2, also known as 2nm GAA, is expected to be used for a lower-end version.

(Photo credit: TSMC)

While Taiwanese foundries are reportedly facing price pressure in mature nodes and are said to be offering discounts, TSMC is also rumored to mull about offering discounts to its customers on mature nodes, particular for 7nm and 14nm, a report by Commercial Times indicates.

Sources cited by the report suggest that the foundry giant’s latest move would be a countermeasure to the competition from Samsung and other Chinese foundries.

A previous report by the Economic Daily News notes that local foundries in Taiwan, such as United Microelectronics Corp. (UMC), Vanguard International Semiconductor Corp. (VIS), and Powerchip Semiconductor Manufacturing Corp. (PSMC), are already offering discounts on mature process orders in the fourth quarter, marking a shift from the relatively stable pricing seen in the third quarter.

Now, TSMC seems to follow suit. The report by Commercial Times indicates that this move will boost capacity utilization for TSMC’s mature processes, while offsetting the risk of declining average selling prices (ASP) due to heated competition.

Looking ahead to next year, the pricing pressure on mature processes will likely persist, as TSMC may lead the way in offering discounts for some of its mature nodes, the report notes. Volume would reportedly play a key role in securing discounts, as TSMC may allow more flexibility in pricing with massive orders.

It is worth noting that Chinese foundries, which had previously been aggressive in cutting prices, have held firm this time. As these companies are struggling to make profit, they have signaled potential price increases, according to the report.

Therefore, it is indicated that certain Taiwanese IC design companies have increased their orders with local foundries. By working on price negotiations with different suppliers, they can further optimize their cost structure.

Sources in the supply chain cited by the report also indicate that in the past, Taiwanese foundries were often forced to follow their Chinese rivals in cutting prices due to aggressive competition. However, as Chinese manufacturers have been gradually balancing their supply and demand, Taiwanese companies hope to seize this opportunity by offering greater pricing flexibility this time, allowing their customers to negotiate based on the volume to expand market share and boost capacity utilization.

The other three major foundries in Taiwan, as mentioned above, had seen their utilization rates rising above 70% in the third quarter, the report suggests. However, if the foundries aim to further increase their capacity utilization, they will inevitably need to move away from the relatively passive order-taking strategies they used to adopt.

In terms of the market demand in 2025, sources from IC design firms cited by the report note that there may still be room for price adjustments. For now, the demand for advanced nodes, which are driven by AI and smartphones, seems to remain solid. However, the demand from automotive and industrial control sectors has yet to show a clear recovery, which may be inferred from the moderate price discounts offered by Taiwanese manufacturers, according to the report.

Read more

• [News] Weak Demand Drags Down Semiconductor Mature Process Pricing, May Decline for Two Quarters

(Photo credit: TSMC)