As the demand for AI GPUs increases, TSMC’s advanced packaging capacity for CoWoS is struggling to keep up. Recently, according to a report from Commercial Times, NVIDIA has reportedly turned to Intel for advanced packaging solutions.

According to industry sources cited by the same report, TSMC’s CoWoS-S and Intel’s Foveros packaging technologies are similar, allowing clients to turn to Intel and secures the capacity needed quickly.

Despite its current struggling on transformation, Intel has been gradually developing its ‘s foundry services. In addition to clients like Qualcomm and Microsoft, Intel’s advanced packaging has also attracted interest from companies like Cisco and AWS.

Under the IDM 2.0 strategy, Intel has opened up its wafer outsourcing and foundry services to customers, establishing an the independent IFS foundry service. Earlier this year, Intel secured a major USD 15 billon foundry order from Microsoft for the first system-level AI foundry service, which is expected to use the Intel 18A process.

The report from Commercial Times further suggested that Microsoft’s move is anticipated to reduce its heavy reliance on TSMC. The report also indicates that chip customers, including NVIDIA, have engaged with Intel. Intel’s flexible foundry strategy, which can provide advanced packaging, software, and chiplet services tailored to customer needs, has been well-received by chipmakers.

Sources cited by the same report reveal that the U.S. has begun allocating specialized funds to increase investments in the advanced packaging sector as well. This move could highlight the importance of advanced packaging as the next key area for global competition in production capacity.

In November last year, the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST) released a report titled “National Advanced Packaging Manufacturing Program,” highlighting that advanced packaging technology is one of the key technologies in semiconductor manufacturing.

Additionally, the U.S. Department of Commerce plans to invest approximately USD 3 billion to advance the National Advanced Packaging Manufacturing Program. Intel, alongside Amkor, is another giant in local advanced packaging in the U.S.

The main focus of advanced packaging is on interconnect density, power efficiency, and scaling. From Foveros to hybrid bonding technology, Intel is gradually scaling down bumping pitch sizes, which allows for higher current loads and better thermal performance.

Furthermore, in May last year, Intel’s advanced packaging technology roadmap outlined plans to transition from traditional substrates to more advanced glass substrates.

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(Photo credit: Intel)

Amid the heating tech war between the U.S. and China, and the stringent sanctions imposed to prevent China from obtaining cutting-edge chips, it appears that China is still able to find its way out. According to a report by Tom’s Hardware, citing the New York Times, the latest tactic of China would be setting up new companies to trade advanced hardware and operating them until they are shut down.

Before that, it is understood that Chinese firms have been smuggling NVIDIA chips through some underground networks, which involve buyers, sellers and dispatchers, according to a previous report by the Wall Street Journals.

Now the country seems to find another option in order to evade the sanctions. According to the New York Times and Tom’s Hardware, buyers that include state-owned or affiliated companies, even sanctioned companies, are reportedly collaborating with the Chinese defense industry, as transactions ranging from a few hundreds of GPUs to a deal worth USD 103 million have been observed lately.

The new tactic, it is reported, would be to establish new companies to acquire advanced chips before facing U.S. sanctions. For instance, after Sugon, established under the strong promotion of the Chinese Academy of Sciences and focuses on fields like computing, storage, security and data center, was banned from obtaining NVIDIA chips due to its ties with the Chinese military, some former executives created a new company named Nettrix.

The reports further note that within six months, Nettrix became one of the largest Chinese manufacturers of AI servers, as tech giants including NVIDIA, Intel, and Microsoft have already begun doing business with it, all without violating any American laws. Given the company’s recent establishment, the U.S. likely hasn’t had the opportunity to thoroughly vet its background.

The reports suggest that the White House might significantly reduce Chinese backdoors in trade by ensuring that only licensed, white-listed buyers can legally procure these chips. However, many in the industry oppose increasingly stringent bans, arguing that they harm American companies more than they help.

Before the upcoming U.S. presidential election in November, the Biden authority is said to be considering a series of actions targeting semiconductors. The latest one includes new measures that might unilaterally impose restrictions on China as early as late August, preventing major memory manufacturers like Micron, SK hynix, and Samsung Electronics from selling high-bandwidth memory (HBM) to China.

• [News] US Reportedly Weighs Stricter Limits on AI Memory Access for China
• [News] China Reportedly Acquires Nvidia AI Chips Indirectly; Nvidia, Gigabyte Emphasize Compliance with U.S. Regulations

(Photo credit: Nettrix)

TSMC’s fan-out (InFO) packaging process will no longer be exclusively used by Apple. According to a report from Commercial Times, it’s revealed that Google’s self-developed Tensor chips for their phones will switch to TSMC’s 3nm process next year and will also start using InFO packaging.

TSMC developed InFO packaging based on FOWLP (fan-out wafer-level packaging), which gained prominence after being adopted by the A10 processor in the iPhone 7 in 2016.

TSMC indicated that the current InFO_PoP technology has advanced to its ninth generation. Last year, it successfully certified 3nm chips, achieving higher efficiency and lower power consumption for mobile devices. The InFO_PoP technology, which features a backside redistribution layer (RDL), has entered mass production this year.

According to industry sources cited by the Commercial Times, Google will shift to TSMC for the Tensor G5 chips, which will be used in the Pixel 10 series next year. These chips will not only utilize the 3nm process but will also adopt integrated fan-out packaging.

This year’s Tensor G4 chips, set to be announced soon, use Samsung’s FOPLP (fan-out panel-level packaging). Although wafer-level packaging (WLP) is generally considered to have advantages over panel-level packaging (PLP), FOWLP still prevails at this stage due to yield and cost considerations.

TSMC has also begun developing FOPLP technology. Previously, per sources cited by a report from MoneyDJ, TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

Although it is not expected to mature within the next three years, major customers like NVIDIA have partnered with foundry companies to develop new materials. One of TSMC’s major clients has already provided specifications for using glass materials.

Traditionally, chip advancements have been achieved through more advanced process nodes. However, new materials could enable the integration of more transistors on a single chip, achieving the same goal of scaling.

For instance, Intel plans to use glass substrates by 2030, potentially allowing a single chip to house one trillion transistors – 50 times the number in Apple’s A17 Pro processor. This suggests that glass substrates could become a significant milestone in chip development.

Another sources cited by Commercial Times have also indicated that glass substrates are part of the medium- to long-term technological roadmap. They can address challenges in large-size, high-density interconnect substrate development.

Currently, this technology is in the early stages of research and development. Its impact on ABF (Ajinomoto Build-up Film) substrates is expected to become significant in the second half of 2027 or later.

Read more

• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road

(Photo credit: TSMC)

The U.S. Bureau of Labor Statistics released the July employment report on August 2, indicating that the unemployment rate increased to 4.3% from 4.1% in June. Although the unemployment rate remains near historical lows and close to the natural rate of unemployment, it has been rising for four consecutive months.

At the same time, nonfarm payrolls increased by only 114,000, significantly below the 12-month average of 215,000. The year-over-year growth in average hourly earnings also declined from 3.8% to 3.6%, continuing its downward trend. Additionally, the number of initial jobless claims continues to rise.

During the July FOMC meeting, the Federal Reserve noted that it would more carefully balance the risks between the labor market and inflation. Fed Chair Jerome Powell also explicitly stated that he did not want to see further cooling in the labor market.

In light of the series of data showing a slowdown in the labor market, the market has started to anticipate more aggressive rate cuts at the September FOMC meeting. According to FedWatch data, the probability of a 50-basis-point rate cut has surged from 11.5% a week ago to 77.5%.

Read more at Datatrack

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(Photo Credit: Pixabay)

According to STDaily citing a recent report on the official website of Okinawa Institute of Science and Technology Graduate University (OIST) in Japan announced that, the university has designed an extreme ultraviolet (EUV) lithography technology that surpasses the standard boundary of semiconductor manufacturing.

Lithography equipment based on such a design can use a smaller EUV light source, consuming less than one-tenth the power of traditional EUV lithography equipment, which can reduce costs and significantly improve the reliability and lifespan of the equipment.

In traditional optical systems, such as camera, telescope, and conventional ultraviolet lithography technologies, optical elements like apertures and lenses are arranged symmetrically along a straight axis. This method is not suitable for EUV rays because their wavelengths are extremely short and most will be absorbed by materials.

Thus, EUV light is guided using crescent-shaped mirrors, but this leads to light deviation from the central axis, sacrificing important optical properties and reducing the overall performance of the system.

To tackle this issue, the new lithography technology achieves its optical properties by aligning two axisymmetric mirrors with tiny central holes in a straight line. Due to the high absorption rate of EUV, each mirror reflection weakens the energy by 40%.

In accordance with industry standards, only about 1% of the EUV light source energy reaches the wafer after passing through 10 mirrors, which requires a very high EUV light output.

In contrast, limiting the number of mirrors from the EUV light source to the wafer to a total of four allows more than 10% of the energy to penetrate the wafer, which can largely bring down power consumption.

The core projector of the new EUV lithography technology, consisting of two mirrors similar to an astronomical telescope, can transfer the light mask image onto the silicon wafer. The team claims this configuration is incredibly simple since traditional projectors require at least six mirrors.

This was achieved by rethinking the theory of optical aberration calibration, and its performance has been verified by optical simulation software, which means it can meet the production requirements of advanced semiconductors.

Besides, the team designed a new type of illumination optical method called “dual-line field” for this novel technology, which uses EUV light to illuminate a plane mirror light mask from the front without interfering with the light path.

Read more

• [News] TSMC Reveals High-NA EUV Equipment Will Be Adopted at the Right Time
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(Photo credit: OIST)