China’s industrial enterprises’ profits saw a significant decline in August, according to data released by the National Bureau of Statistics on September 27. In August, industrial profits fell by 17.8% year-over-year, a sharp decline from July’s 4.1% increase, marking a 21.9 percentage point decrease and the largest drop so far this year, ending two consecutive months of accelerating growth. From January to August, the cumulative annual growth rate of profits for industrial enterprises above a designated size was 0.5%, down from 3.6% in the January-to-July period, representing a 3.1 percentage point decrease.

National Bureau of Statistics industrial statistics expert Yu Weining stated that the sharp decline was mainly driven by insufficient domestic demand and the impact of extreme weather conditions. High-tech manufacturing, a key profit driver, also experienced a decline in August, with cumulative growth for January to August at 10.9%, down from 12.8% in the January-July period. Additionally, profits in sectors such as mining and consumer goods manufacturing continued to shrink, further exacerbating the downward pressure on overall industrial profits.

Facing Economic Growth Challenges, PBOC Unveils a Series of Solutions：

In response to a series of weak economic data, the People’s Bank of China (PBOC) introduced a range of easing policies on September 24, targeting interest rates, real estate, and the stock market.

Interest rate: The PBOC lowered the reserve requirement ratio for financial institutions by 0.5 percentage points, bringing the weighted average reserve ratio down from 7% to 6.6%. The central bank indicated it would continue to monitor market conditions and could reduce the ratio further by 0.25 to 0.5 percentage points if necessary. Additionally, the PBOC’s main policy rate, the 7-day reverse repurchase rate, will be reduced from 1.7% to 1.5% to guide market lending rates (LPR) lower.

Real Estate: The PBOC will direct commercial banks to lower mortgage rates by 0.5 percentage points and reduce the down payment ratio for second homes from 25% to 15%. Furthermore, for the 300-billion-yuan in affordable housing re-lending established in May, the PBOC will increase its support ratio from 60% to 100%.

Stock Market: The PBOC will allow securities, funds, and Insurance firm to pledge assets to the central bank in exchange for liquidity. Additionally, the PBOC has introduced a share repurchase and equity increase loan facility to provide listed companies with funding for share buybacks and equity increases.

Overall, as global demand weakens and exports hard to sustain the national economy, the PBOC implemented a more aggressive easing policy just days after the U.S. Federal Reserve’s rate cut. This move aims to mitigate the risks of RMB depreciation and capital outflows, while slightly alleviating the pressure to meet economic growth targets.

Read more at Datatrack

Amid an operational crisis, Intel has abandoned its “5 Nodes in 4 Years” plan, shelving the Intel 20A process node to focus entirely on the more advanced Intel 18A. Now, there is finally good news regarding the 18A process.

During the recent Enterprise Tech Tour in Portland, Oregon, CEO Pat Gelsinger made the first public reveal of the Clearwater Forest Xeon server processor, produced using the Intel 18A node. This chip is a crucial element in determining whether Intel’s ambitious transformation plan will succeed, according to Tom’s Hardware.

The report highlights that Clearwater Forest is the first high-volume chip to be fabricated on the Intel 18A node—a process so pivotal that Gelsinger has effectively staked the entire company’s future on its success. Although the chip was showcased at the event, it won’t hit the market until next year.

Tom’s Hardware also notes that while Intel will manufacture a range of other processors on the 18A node, delivering the Clearwater Forest chips on schedule is critical to restoring confidence in Intel’s foundry business among potential customers. This node is key to Gelsinger’s larger turnaround strategy, representing the culmination of his bold yet desperate push to develop five nodes in four years to revive Intel’s fortunes.

At the same event, Intel also introduced its Granite Rapids Xeon chips for data centers, boasting core counts that finally match those of AMD’s EPYC processors—an achievement Intel has struggled to reach since EPYC’s debut in 2017.

(Photo credit: Intel)

With silicon photonics emerging as a key enabler in the AI era, semiconductor giants have been accelerating their deployment in the technology. Now TSMC announces its latest breakthrough. According to a press release, by collaborating with EDA solution provider Ansys, the foundry leader has achieved over 10X speed-up of photonics simulation, powered by NVIDIA’s GPUs running on the Azure AI infrastructure of Microsoft.

Silicon PIC is a type of optical communications that enables data to travel farther and faster, which can be integrated to hyperscale data centers and IoT applications.

However, combining photonic and electronic circuits is a painstaking task requiring precise multiphysics design and fabrication. A minor misstep can create continuity challenges within chips, which can result in additional cost and timeline setbacks up to several months.

Therefore, to address challenges and harness the ultra-bandwidth potential of silicon PICs, TSMC partnered with Ansys to accelerate Lumerical FDTD simulations by leveraging Azure virtual machines powered by NVIDIA GPUs.

The press release notes that these Azure NC A100v4 VMs could facilitate the simulations, optimizing resources to achieve a cost-effective balance between performance and expense. Together, the companies achieved over 10X speed-up of Ansys Lumerical FDTD photonics simulation.

Moreover, running Lumerical FDTD simulations in the cloud allows designers to quickly identify optimal chip designs while addressing the multiphysics challenges of integrating photonic and electronic circuits, according to the press release.

It is worth noting that silicon photonics has been one of TSMC’s major focus in recent years. A previous report by Nikkei notes that TSMC aims to ready next-gen silicon photonics for AI in 5 years.

At the launch event of the Silicon Photonics Industry Alliance (SiPhIA) in early September, K.C. Hsu, Vice President of Integrated Interconnect & Packaging at TSMC, stated that with the massive computing demands and the large-scale data transmission in the AI era, silicon photonics plays an increasingly vital role, according to a report by the Economic Daily News.

Citing internal TSMC data, Hsu noted that by 2030, AI cloud services are expected to consume 3.5% of the world’s energy. However, with the assistance of silicon photonics and the co-packaged optics (CPO) technology, which is an advanced heterogeneous integration of optics and silicon on a single packaged substrate, the energy consumption per unit can be further reduced, according to the report.

Earlier in April, TSMC has announced that the company is developing Compact Universal Photonic Engine (COUPE) technology, which uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

According to its press release, TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Read more

• [News] Silicon Photonics Reshapes the Future; TSMC, ASE Ready to Seize Market Share
• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: Ansys)

Powerchip Semiconductor Manufacturing Corp. (PSMC) announced on the 26th that it has signed a definitive agreement with Tata Electronics in New Delhi to collaborate on building India’s first 12-inch wafer fab in Dholera, Gujarat. PSMC will transfer mature process technologies and train local employees as part of the partnership.

According to PSMC, the $11 billion facility, with a monthly capacity of 50,000 wafers, is expected to create over 20,000 high-tech jobs in the region.

PSMC Chairman Frank Huang and CEO Martin Chu also met with Indian Prime Minister Narendra Modi at the Prime Minister’s Office. Huang urged Modi to foster a business-friendly environment for Taiwanese companies investing in India, highlighting the vast potential for collaboration between Taiwan and India in the semiconductor space. He noted that the semiconductor supply chain involves thousands of small and medium-sized enterprises, and expressed hope for future partnerships between Taiwanese chip designers and India’s talent-rich market.

Prime Minister Modi, in PSMC’s announcement, pledged full government support for the Tata-PSMC wafer fab project and praised Huang’s vision of Taiwan-India cooperation in the chip design industry. He encouraged PSMC to play a key role in India’s semiconductor development and promised to assist Taiwanese businesses looking to invest in the country.

(Photo credit: PSMC)

As rumors indicate that Samsung plans to withdraw personnel from its USD 40 billion Taylor, Texas plant, a recent report by The Korea Herald dismisses the speculation. Citing a local economic development chief, the report notes that construction is on track to be finished by mid-2025, and the withdrawal of employees are simply routine rotations.

Quoting Dave Porter, executive director at the Williamson County Economic Development Partnership, the report suggests that Samsung regularly rotates its employees every two years so that they can return to Korea, while another group of workforce has taken their place.

Samsung’s initial projection, announced in 2021 when the investment plan was disclosed, had anticipated the Taylor plant to start its mass production of 4nm in the second half of 2024. But afterwards, the tech giant has reportedly postponed the schedule to 2025, as a previous report by U.S. local media MySA noted that the plant may not begin operations until 2026.

The postponement, according to The Korea Herald, may be primarily attributed to a market downturn.

Regarding the node featured in Samsung’s Taylor facility, another report by Wccftech notes that it was initially expected to produce chips with advanced processes below the 4nm node. The company is reportedly mulling to update its fabrication capabilities in the Taylor fab from 4nm to 2nm, while low yields remain a major obstacle.

Despite the scenario, Porter notes that the construction of Samsung’s Taylor plant is moving ahead rapidly, with around 6,000 workers on-site daily. He estimates that the first fabrication plant will be completed between early and mid-2025, with production kicking off sometime between early and mid-2026, in line with Samsung’s forecast.

According to the report, Samsung expects around 150 suppliers to relocate to Texas to support the new fab’s operations. However, for now, many of the suppliers have scaled back their preparations since early this year, following Samsung’s adjusted timeline.

South Korean-based engineering company Hanyang ENG and semiconductor material supplier Soulbrain are among Samsung’s key suppliers in Taylor, Texas, the report indicates.

Read more

• [News] Samsung Reportedly Buckling Under Pressure, with Plans to Cut Overseas Workforce by Up to 30%
• [News] Samsung Reportedly Suspends Construction and Contract Plans for Pyeongtaek P4 and Taylor Plant 2

(Photo credit: Samsung)