To overcome the restrictions from the US and its allies, China is said to be heavily investing in semiconductor development. According to a report from Liberty Times Net, Huawei has completed its “Lianqiu Lake R&D Center” with a total investment exceeding CNY 10 billion (approximately USD 1.4 billion).

EE Times China further reported that Huawei’s “Lianqiu Lake R&D Center,” covering an area of 2,400 acres and a total construction area of 2.06 million square meters, has finally unveiled its mysterious veil after three years of construction.

This research center is designed with 40,000 offices and is expected to gradually attract about 35,000 Huawei R&D talents. It is divided into eight zones, with fully connected internal roads, a miniature train system, and elevated bridges. The park’s transportation includes a miniature train system with a total of eight stations. Once fully completed, Huawei plans to relocate its existing Shanghai R&D base in Jinqiao and other scattered office spaces to the ” Lianqiu Lake R&D Center.”

According to the reported plan, the R&D Center will consolidate Huawei’s research efforts in HiSilicon, wireless technology, flagship smartphone development, smart driving/automotive components, digital energy, and other areas. This move aims to provide advantageous support for Huawei’s expanding businesses such as 5G/6G, digital energy, and smart automotive solutions.

Regarding Huawei’s substantial investment in building this research center, tech media outlet “Tom’s Hardware” highlighted on July 14th that amid the US-China semiconductor rivalry and various US sanctions against Huawei, the company must bolster its research and development efforts. Consolidating multiple research centers allows Huawei to streamline operations and facilitate easier collaboration among different departments.

The report states that this flagship project showcases Huawei’s investment commitment in future technologies. The “Lianqiu Lake R&D Center” is larger in scale than the combined size of Apple Park and Microsoft’s Redmond Campus headquarters in Seattle.

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(Photo credit: Huawei)

According to the industry sources cited in a report from Economic Daily News, TSMC is gearing up to start production of NVIDIA’s latest Blackwell platform architecture graphics processors (GPU) on the 4nm process. In response to the strong customer demand, NVIDIA has reportedly increased its orders to TSMC by 25%.

This surge not only underscores the unprecedented boom in the AI market but also provides substantial momentum for TSMC’s performance in the second half of the year, setting the stage for an optimistic annual outlook adjustment, the report notes.

TSMC is set to hold an earnings conference call on July 18, in which it is expected to release the financial results of the second quarter as well as the guidance for the third quarter.

As TSMC will reportedly commence the production of NVIDIA’s Blackwell platform architecture GPU, which may be regarded as one of the most powerful AI chips, it is anticipated to be a focal point of discussion at TSMC’s upcoming earnings call.

Packed with 208 billion transistors, NVIDIA’s Blackwell-architecture GPUs are manufactured using a custom-built 4NP TSMC process with two-reticle limit GPU dies connected by 10 TB/second chip-to-chip link into a single, unified GPU.

The report further cited sources, revealing that international giants such as Amazon, Dell, Google, Meta, and Microsoft will adopt the NVIDIA Blackwell architecture GPU for AI servers. As demand exceeds expectations,NVIDIA is prompted to increase its orders with TSMC by approximately 25%.

As NVIDIA ramps up production of its Blackwell architecture GPUs, shipments of terminal server cabinets, including the GB200 NVL72 and GB200 NVL36 models, have seen a simultaneous significant increase. Initially expected to ship a combined total of 40,000 units, this figure has surged to 60,000 units, marking a 50% increase. Among them, the GB200 NVL36 accounts for the majority with 50,000 units.

The report estimates suggest that the average selling price of the GB200 NVL36 server cabinet is USD 1.8 million, while the GB200 NVL72 server cabinet commands an even higher price of USD 3 million. The GB200 NVL36 features 36 GB200 super chips, 18 Grace CPUs, and 36 enhanced B200 GPUs, whereas the GB200 NVL72 boasts 72 GB200 super chips, 36 Grace CPUs, and 72 B200 GPUs, which all contribute to TSMC’s momentum.

TSMC former Chairman Mark Liu, before handing over the reins in June, had already predicted that the demand for AI applications looks more optimistic compared to a year ago. Current Chairman C.C. Wei has also indicated that AI applications are just beginning, and he is optimistic like everyone else.

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(Photo credit: TSMC)

Global semiconductor giants are concentrating their R&D efforts on advanced packaging technologies to drive performance enhancements. According to a report from Commercial Times, as packaging technology progresses from 2.5D to 3D, chip stacking technologies have become a showcase for the competitive prowess of major companies.

“Hybrid Bonding” is seen as the key technology for future chip connections. In addition to international companies like Applied Materials and Besi actively positioning themselves, Taiwanese companies led by TSMC, including Gallant Micro, MPI Corporation, E&R Engineering Corporation, C SUN, Saultech, and Grand Process Technology, are also developing and seizing opportunities in Hybrid Bonding.

The report also cited industry sources, pointing out that Grand Process Technology has been supplying TSMC since the inception of InFO (Integrated Fan-Out Packaging). It is revealed that Grand Process Technology is also actively participating in future SoIC (System on Integrated Chips) advanced packaging, focusing on wafer cleaning and photoresist removal in etching processes.

It is indicated by the report that Grand Process Technology’s capacity will be operating at full speed until the first quarter of next year, with lead times extended to nine months. Last year’s orders are currently being installed gradually, with most concentrated on advanced packaging.

Semiconductor equipment manufacturer C SUN and its investment company Gallant Micro are currently investing in Hybrid Bonding-related equipment. C SUN primarily focuses on developing the best solutions for permanent bonding to enhance yield rates. Meanwhile, Gallant Micro leverages its relative advantage in chip sorting machines within its product line.

MPI Corporation, a testing interface vendor, has also entered the initial stages of inspection and analysis for Hybrid Bonding processes. Development of related products is nearing completion.

E&R Engineering Corporation also emphasizes that its top-tier plasma cleaning equipment is currently aimed at achieving high cleanliness of bonding surfaces to enhance adhesion.

Saultech Technology holds a positive outlook on the future market trends of Hybrid Bonding as well. The company has introduced equipment that corresponds to both Hybrid Bonding and Fan-Out technologies. Saultech has independently developed key technologies including bonding and die cleaning processes.

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(Photo credit: Applied Materials)

Chul Joo Hwang, Chairman of South Korean semiconductor equipment company Jusung Engineering, recently stated that future semiconductors will stack transistors together, as the expansion of DRAM and logic chips has reached its limit. Stacking transistors like NAND is necessary to overcome these challenges.

According to a report from South Korean media outlet The Elec, Hwang believes this means developing more atomic layer deposition (ALD) technology to reduce the use of extreme ultraviolet (EUV) lithography steps in the production process of advanced chips.

ALD technology is a thin film process that allows materials to grow layer by layer, offering high uniformity, precise thickness control, and excellent step coverage, overcoming challenges faced by traditional process technologies.

Reportedly, stacking transistors can reduce the need for further scaling of transistors. As evidence, deep ultraviolet (DUV) equipment is expected to be used in 3D DRAM production.

Hwang believes that as stacking becomes increasingly important, the demand for ALD equipment will also rise. Additionally, the production of III-V semiconductors and IGZO semiconductors requires ALD equipment.

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(Photo credit: Jusung Engineering)

X-Epic, a prominent Chinese electronic design automation (EDA) start-up, is said to be reducing its workforce by up to 50%, according to a report by South China Morning Post. As chip design is an indispensable part to semiconductor manufacturing, the incident raises concerns about China’s push for technological self-reliance.

X-Epic, founded in 2020 by Wang Libin, a former engineer at US EDA leader Cadence Design Systems, has been established with the goal of creating indigenous EDA tools to challenge the dominance of US rivals. The field is traditionally governed by US giants including Cadence, Synopsys, and Mentor Graphics (now owned by Siemens).

Based on the definition by Cadence, EDA encompasses software, hardware, and essential services used in the design of chips and semiconductor devices. Historically, hardware architects sketched chip designs by hand and used isolated tools. However, alongside the rapid growth of AI, EDA has become indispensable as chip designs get complicated. The tool provides a simulated environment where circuits and designs are conceived and analyzed before being realized in the physical world.

According to the report, as of March, 2023, X-Epic employed approximately 400 people across offices in Nanjing, Beijing, Shanghai, Chengdu, and Shenzhen. However, the company began laying off up to half its employees recently across various departments, including its key research and development division.

The report further analyzes that in In August 2022, Washington first restricted China’s access to the EDA technology by prohibiting the export of gate all-around (GAA) capable EDA software, which creates challenges for Chinese chipmakers in adopting advanced processes such as the 3nm node and in developing high-performance computing or AI chips.

Citing data from the China Semiconductor Industry Association, the report notes that the value of China’s EDA market is projected to reach 18.5 billion yuan (USD 2.55 billion) next year, up from 9.3 billion yuan in 2020. As the market seems to be booming, X-Epic’s reported layoff highlights the challenges China’s EDA companies are facing.

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(Photo credit: X-Epic)