According to Reuters citing sources, Intel, facing a critical survival crisis, has temporarily halted its new chip packaging and testing project in Penang.

Malaysian media outlet The Star, citing informed sources, reported that Intel will temporarily halt its new chip packaging and testing project in Penang as part of cost-cutting efforts. However, the operations of existing facilities will remain unaffected.

The U.S. chip giant had announced three years ago that it would invest approximately USD 7 billion to build new chip packaging and testing facilities in Malaysia, looking to make it its largest overseas packaging and testing base.

Facing what is described as the most challenging period in its 56-year history, Intel is making drastic survival moves, including suspending dividend payments and laying off 15% of its global workforce to significantly reduce expenses.

Per The Star, Intel employs around 14,000 people in Malaysia, meaning over 2,000 local employees may face the risk of job loss.

Three weeks ago, Penang Chief Minister Chow Kon Yeow stated that Intel would continue its expansion plans in Penang, though he admitted that Intel’s USD 10 billion cost-cutting initiative would inevitably impact its operations in the region.

The Star cited sources, pointing out that Intel has been reassessing its investment projects in Malaysia. While construction at its new facility in Penang is still ongoing, the number of workers has been reduced.

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(Photo credit: Intel)

The U.S. non-farm payroll data for August is set to be released on September 6. Ahead of that, the ADP employment report, often referred to as the “mini-NFP,” was published on September 5. The report revealed that private-sector employment in the US rose by 99,000 jobs in August, significantly lower than the market expectation of 145,000, marking the lowest level since 2021 and signaling a further slowdown in the labor market. This has heightened speculations that the Federal Reserve might increase the scale of rate cuts.

The ISM Services PMI, which was released on the same day, presented a more optimistic picture. The August Services PMI came in at 51.5 (previously 51.4), slightly higher than the market expectation of 51.3, remaining in expansion territory for the second consecutive month.

Breaking down the sub-indices, the employment index fell to 50.2 (previously 51.1), in line with the ongoing labor market slowdown but still indicating growth. The new orders index rose to 53.0 (previously 52.4), and the supplier delivery time index increased to 49.6 (previously 47.6), reflecting continued strong demand for services. However, the business activity index dropped to 53.3 (previously 54.5), suggesting that high interest rates and costs are still exerting some negative pressure on business operations. Despite this, all indices remained in expansion, indicating that the overall services sector is still experiencing stable growth.

Read more at Datatrack

In the commentary from managers surveyed, industries with rising demand (such as finance, information, entertainment, and healthcare) reported continued improvement or strength in business activity. Conversely, sectors with declining demand (such as construction, utilities, and wholesale trade) cited high interest rates and cost pressures as factors weakening business activity. Some companies in these sectors are also conducting layoffs or reducing hiring. Overall, while the demand in the services sector is significantly stronger than in manufacturing, there are still signs of uneven recovery across industries.

Read more at Datatrack

Amid the rising of emerging applications in the AI market, the booming demands for high-performance computing (HPC), high-bandwidth memory (HBM), CoWoS advanced packaging, and high-performance storage, have energized the wafer foundry industry.

Given the broader applicability of 12-inch wafer in advanced process chips, the global expansion of 12-inch wafer production has accelerated in recent years. Leading companies like TSMC, Intel, UMC, Vanguard International Semiconductor (VIS), SMIC, and Huahong have successively released production capacity.

• VIS’ Singapore 12-Inch Fab Got Approved

On September 4, VIS and NXP jointly announced the approval of their Singapore-based 12-inch wafer fab joint venture by regulatory authorities in Taiwan, Singapore, and other regions.

The joint venture, named VisionPower Semiconductor Manufacturing Company (VSMC), will begin construction of its first 12-inch (300mm) wafer fab in the second half of this year.

VIS estimates that trial production will begin in 2027, with profitability expected by 2029. TSMC will provide technological support, and the market holds a favorable long-term outlook for the company’s operations.

Upon its mass production, both companies may consider building a second fab. Currently, VIS operates five 8-inch fabs located in Taiwan and Singapore. Three of the 8-inch fabs are in Hsinchu, and one in Taoyuan. The average monthly capacity of its 8-inch fabs in 2023 was about 279,000 wafers.

• TSMC Expands Production Worldwide

On August 20, TSMC held a groundbreaking ceremony for its new German fab, ESMC, which is set to begin construction by the end of the year and aims to start production by the end of 2027.

The project involves an investment of over EUR 10 billion and is expected to have a monthly capacity of 40,000 12-inch wafers, utilizing TSMC’s 28/22nm planar CMOS and 16/12nm FinFET process technologies.

In early September, Taiwan’s Ministry of Economic Affairs announced that TSMC plans to build a third fab in Japan to produce advanced semiconductors, with construction expected after 2030.

TSMC’s first fab in Kumamoto, Japan, officially opened on February 24, 2023, and will begin mass production in Q4 this year using 28/22nm and 16/12nm process technologies, with a monthly capacity of 55,000 wafers.

The second fab in Kumamoto is planned, with construction expected to start by the end of this year and operations to begin by the end of 2027, targeting 6/7nm nodes.

Additionally, TSMC’s 2nm fabs in Hsinchu (Fab 20) and Kaohsiung (Fab 22) in Taiwan are scheduled to start mass production next year.

In the U.S., TSMC’s first fab in Arizona is scheduled to begin producing chips using 4nm technology in the first half of 2025. The second fab will produce both 3nm and 2nm chips using next-generation nanosheet transistors, with production starting in 2025.

Plans for a third fab are also underway, with production of chips using 2nm or more advanced processes expected to begin in 2028.

• UMC’s Fab 12i in Singapore has Set Equipment in Place

On May 21, UMC held a ceremony for the settlement of equipment at its expanded Fab 12i in Singapore with the arrival of the first equipment.

UMC has operated 12-inch fabs in Singapore for over 20 years, and in February 2022, it announced the plan to invest USD 5 billion to expand Fab 12i, adding a new 12-inch fab with a monthly capacity of 30,000 wafers, focusing on 22/28nm processes. Mass production is expected by early 2026.

• Toshiba’s 12-Inch Wafer Fab Completed

On May 23, Toshiba Electronic Devices & Memory Corporation announced the completion of its new 300mm power semiconductor manufacturing fab, with a total investment of JPY 100 billion and plans to begin production in March 2025.

The fab will be built in two phases, with the first phase starting production within the 2024 fiscal year. Once fully operational, Toshiba’s power semiconductor capacity will be 2.5 times that of 2021. Equipment installation is underway, with mass production expected in the second half of FY2024.

• Powerchip Begins Construction of Two New 12-Inch Fabs

On March 13, Powerchip held a groundbreaking ceremony for a 12-inch wafer fab in partnership with India’s Tata Group, located in Dholera, Gujarat, with a total investment of INR 910 billion rupees (about USD 11 billion).

The fab will have a monthly capacity of 50,000 wafers and will produce chips using 28nm, 40nm, 55nm, 90nm, and 110nm nodes.

In early May, Powerchip also announced plans for a new 12-inch fab to expand advanced packaging capacity to support growing demand for AI devices. Powerchip’s chairman stated that the company will provide interposers, one of the three components in CoWoS packaging technology.

• Texas Instruments Built Three New 12-Inch Fabs

Texas Instruments is currently expanding its 300mm capacity to meet future demand for analog and embedded processing chips. TI plans to invest USD 30 billion in building up to four interconnected fabs (SM1, SM2, SM3, SM4) in the coming decades.

According to its 2022 roadmap, TI will build six 300mm fabs by 2030, with RFAB2 in Richardson, Texas, and LFAB (acquired from Micron) already starting production in 2022 and 2023, respectively. Two of the Sherman fabs were completed in 2023, with two more planned for 2026-2030.

In addition to the plan mentioned above, TI also announced the plan for a second 300mm fab in Lehi, Utah in February 2023, adjacent to its existing 12-inch fab, with production estimated to begin in 2026, focusing on producing analog and embedded processing chips. These fabs will be combined into one once the construction is completed.

On August 16, Texas Instruments announced that it received USD 1.6 billion in funding from the U.S. CHIPS Act. This funding will be used to build a cleanroom for the SM1 fab and complete the pilot production line, construct a cleanroom for LFAB2 to begin initial production, and build the shell for the SM2 fab.

• Intel Focuses on U.S. Projects in Arizona and Ohio

Intel has disclosed chip expansion plans in multiple regions, including Arizona, New Mexico, Ohio, Oregon, Ireland, Israel, Magdeburg, Malaysia, and Poland. However, due to market challenges and poor financial results, some of Intel’s expansion plans have been delayed.

Currently, Intel is advancing the construction of large semiconductor manufacturing plants in Arizona and Ohio for the production of cutting-edge semiconductors, as well as working on equipment development and advanced packaging projects at smaller facilities in Oregon and New Mexico.

• GlobalFoundries Revved up Investment in the U.S. and Portugal

On February 19, the U.S. government announced a USD 1.5 billion subsidy for GlobalFoundries. According to a preliminary agreement with the U.S. Department of Commerce, GlobalFoundries will establish a new semiconductor manufacturing facility in Malta, New York, and expand its existing Fab 8 plant in the same location.

The facility will leverage manufacturing technology already implemented in GlobalFoundries’ plants in Germany and Singapore to produce automotive chips, effectively introducing mature-node technology into Fab 8.

In February of this year, GlobalFoundries also announced a partnership with Amkor Technology to build a large packaging facility in Portugal.

It plans to transfer the 12-inch wafer-level packaging production line from its Dresden plant to Amkor’s facility in Porto, Portugal, aiming to establish Europe’s first large-scale backend facility. GlobalFoundries will retain ownership of the tools, processes, and IP transferred to Porto.

• China’s 12-Inch Wafer Production Lines Entered New Stages

In China, companies like SMIC, Huahong, CR Micro (Shenzhen), and Zensemi (Guangzhou) are making new progresses in 12-inch wafer production.

SMIC expects its monthly 12-inch wafer capacity to increase by 60,000 by the end of the year.

Huahong is speeding up the construction of its new 12-inch fab in Wuxi, with the first lithography machine installed on August 22, aiming for production in 1Q24.

CR Micro’s 12-inch fab in Shenzhen has entered the stage of equipment installation and debugging, with production expected to start in late 2024.

Zensemi’s 12-inch wafer manufacturing production line has went into production.

Read more

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(Photo credit: TSMC)

At the SEMICON Taiwan 2024, Samsung’s Head of Memory Business, Jung Bae Lee, stated that as the industry enters the HBM4 era, collaboration between memory makers, foundries, and customers is becoming increasingly crucial.

Reportedly, Samsung is prepared with turnkey solutions while maintaining flexibility, allowing customers to design their own basedie (foundation die) and not restricting production to Samsung’s foundries.

As per anue, Samsung will actively collaborate with others, with speculation suggesting this may involve outsourcing orders to TSMC.

Citing sources, anue reported that SK hynix has signed a memorandum of understanding with TSMC in response to changes in the HBM4 architecture. TSMC will handle the production of SK hynix’s basedie using its 12nm process.

This move helps SK hynix maintain its leadership while also ensuring a close relationship with NVIDIA.

Jung Bae Lee further noted that in the AI era, memory faces challenges of high performance and low energy consumption, such as increasing I/O counts and faster transmission speeds. One solution is to outsource the basedie to foundries using logic processes, then integrate it with memory through Through-Silicon Via (TSV) technology to create customized HBM.

Lee anticipates that this shift will occur after HBM4, signifying increasingly close collaboration between memory makers, foundries, and customers. With Samsung’s expertise in both memory and foundry services, the company is prepared with turnkey solutions, offering customers end-to-end production services.

Still, Jung Bae Lee emphasized that Samsung’s memory division has also developed an IP solution for basedie, enabling customers to design their own chips. Samsung is committed to providing flexible foundry services, with future collaborations not limited to Samsung’s foundries, and plans to actively partner with others to drive industry transformation.

Reportedly, Samsung is optimistic about the HBM market, projecting it to reach 1.6 billion Gb this year—double the combined figure from 2016 to 2023—highlighting HBM’s explosive growth.

Address the matter, TrendForce further notes that for the HBM4 generation base die, SK hynix plans to use TSMC’s 12nm and 5nm foundry services. Meanwhile, Samsung will employ its own 4nm foundry, and Micron is expected to produce in-house using a planar process. These plans are largely finalized.

For the HBM4e generation, TrendForce anticipates that both Samsung and Micron will be more inclined to outsource the production of their base dies to TSMC. This shift is primarily driven by the need to boost chip performance and support custom designs, making further process miniaturization more critical.

Moreover, the increased integration of CoWoS packaging with HBM further strengthens TSMC’s position as it is the main provider of CoWoS services.

Read more

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(Photo credit: TechNews)

Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, stated that 3D IC is a crucial method for integrating AI chip memory with logic chips.

According to a report from TechNews, regarding the development of 2.5D CoWoS advanced packaging, which integrates eight chiplets, TSMC will use the A16 advanced process to manufacture the chiplets, and integrated them with 12 HBM4, which is expected to be launched in 2027.

Reportedly, in his speech at the Semicon Taiwan 2024 “3D IC / CoWoS for AI Summit,”  He noted that the global semiconductor market is projected to become a trillion-dollar industry by 2030, with HPC and AI being the key drivers, accounting for 40% of the market, which also make AI chips crucial drivers for 3D IC packaging.

The reasons customers choose to manufacture AI chips with 3D IC platform for multi-chiplet design would be related to their lower costs and reduced design transition burdens.

Jun He explained that by converting a traditional SoC+HBM design to a chiplet and HBM architecture, the new logic chip would be the only component that needed to be designed from scratch, while other components such as I/O and SoC can use existing process technologies. This approach reduces mass production costs by up to 76%.

Although the new architecture might increase production costs by 2%, the total cost of ownership (TCO) is improved by 22% due to these efficiencies, He noted.

However, 3D IC still faces challenges, particularly in increasing production capacity. Jun He emphasized that the key to enhancing 3D IC capacity lies in the size of the chips and the complexity of the manufacturing process.

Regarding chip size, larger chips can accommodate more chiplets, improving performance. However, this also increases the complexity of the process, which can be three times more challenging. Additionally, there are risks associated with chip misalignment, breakage, and failure during extraction.

To address these risk challenges, Jun He identified three key factors: tool automation and standardization, process control and quality, and the support of the 3DFabric manufacturing platform.

For tool automation and standardization, TSMC’s differentiated capabilities with its tool suppliers are crucial. With 64 suppliers now involved, TSMC has gained the ability to lead in advanced packaging tools.

In terms of process control and quality, TSMC utilizes high-resolution PnP tools and AI-driven quality control to ensure comprehensive and robust quality management. Finally, the 3DFabric manufacturing platform integrates 1,500 types of materials within the supply chain to achieve optimization.

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• [News] TSMC Plans Rapid CoWoS Expansion Through 2026 in Response to Client Demand
• [News] TSMC Rumored to Build New CoWoS Plant in Southern Taiwan

(Photo credit: TSMC)