With advanced packaging capacity at TSMC being tight, the expansion of CoWoS has garnered significant attention. According to a report from Economic Daily News, Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, noted at SEMICON Taiwan 2024 that the foundry giant is rapidly expanding its advanced packaging capacity to meet customer demands.

The company expects CoWoS capacity to grow at a compound annual growth rate of over 50% from 2022 to 2026, with high-speed expansion continuing at least until 2026.

During Jun He’s keynote at the “3D IC/CoWoS for AI Summit – HIGS Series Event” on September 4, He joked that due to severe supply shortages, he refrained from including numbers in his presentation, as customer complaints about insufficient capacity were frequent.

In response to strong customer demand, Jun He revealed that TSMC will continue to rapidly expand its advanced packaging capacity through 2026, with increased construction speeds. For CoWoS capacity, the time to build an advanced packaging plant has been reduced from three to five years to within two years, or even a year and a half.

He noted that the strong demand for advanced packaging is driven by the cost reduction benefits of chiplet design. The successful development of chiplets relies on advanced packaging, prompting TSMC to actively promote the 3DFabric Alliance to accelerate innovation and development within the 3D IC ecosystem.

Mike Hung, Senior Vice President of ASE echoed Jun He’s views, noting that the industry has learned valuable lessons from the 2.5D packaging sector since its mass production in 2013. ASE has been partnering with TSMC to boost their CoWoS capacities.

He added that further standardization of equipment or materials would be advantageous for accelerating industry innovation.

Take panel-level packaging as an example, he noted that while the technology could help  increased efficiency thanks to the transition from round to square substrates, it also presents challenges in areas like equipment and materials.

Jun He added that advancing packaging requires efforts from partners in advanced packaging materials and HBM to drive progress collectively.

On the other hand, DJ Lee, Director and COO of PCB leader ZDT Group, suggested that as the industry progresses, packaging substrates will trend towards higher layers, larger areas, flatness, and precise designs. To meet the semiconductor-level requirements, substrate manufacturers will need to enhance their smart manufacturing capabilities.

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• [News] TSMC Rumored to Build New CoWoS Plant in Southern Taiwan
• [News] TSMC Halts Chia-Yi Plant Construction Due to Relic Found, Quickly Initiates Preparation for 2nd Plant

(Photo credit: TSMC)

Disappointing financial results. A 15% layoff of its workforce. Restructuring and cost-reduction plans which may include the sale of FPGA unit Altera and freezing its USD 32 billion German fab project. Now, there seems to be more bad news on the way for Intel, as its advanced nodes, specifically 18A and 20A, reportedly run into trouble.

Broadcom Regards 18A Not Ready for High-volume Production

According to Reuters and The Verge, Broadcom’s initial tests with Intel’s 18A (1.8nm-class) process did not meet expectations, creating additional pressure on the semiconductor giant’s efforts to catch up with TSMC in the foundry sector. The reports note that Broadcom tested Intel’s 18A by producing wafers with typical design patterns. However, its engineers and executives were said to be disappointed with the results, regarding the process as “not ready for high-volume production.”

A Broadcom spokesperson informed Reuters that the company has not yet completed its evaluation of Intel’s 18A, indicating that the assessment is still in progress.

The 18A node plays a crucial role in Intel’s roadmap, as it has been working on the process for years, targeting to begin mass production next year, with major clients including Microsoft, according to the Verge.

However, another report from Tom’s Hardware also suggests that a defect density below 0.5 defects per square centimeter is typically seen as a positive outcome, which Intel may have already accomplished. Citing CEO Pat Gelsinger’s previous remarks, the report notes that Intel is now below 0.4 d0 defect density, which can be considered a healthy process.

20 A Cancelled: Not a Bad Idea for Cost-reduction?

Another latest bad news, though, is that Intel announced that it will no longer use its own 20A process for the upcoming Arrow Lake processors aimed at the consumer market. In its own words, the Arrow Lake processor family will be built primarily using external partners and packaged by Intel Foundry.

The unexpected move, according to Intel, is made in order to focus resources on Intel 18A, helping the company to optimize its engineering investments.

The strategy might not be a bad idea amid Intel’s crisis, as the bypass of the 20A process altogether can help avoiding the significant capital expenditures needed to scale the node to full production, a report by Tom’s Hardware notes. By sidestepping the typically high costs associated with ramping up a new and advanced node like 20A, the company will likely make progress toward its cost-cutting objectives. The order of Arrow Lake, though, might possibly go to TSMC, the report indicates.

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• [News] AMD Could Emerge as a Prospective Buyer for Intel’s Potential Sale of Altera
• [News] Intel Reportedly Mulls to Sell FPGA Unit Altera and Freeze USD 32 Billion German Project amid Crisis

(Photo credit: Intel)

SK hynix President Justin Kim shared insights on SK hynix’s current memory products and HBM-related offerings in a speech titled “Unleashing the Possibilities of AI Memory Technology.” Per a report from TechNews, he announced at Semicon Taiwan that the company would begin mass production of 12-stack HBM3e by the end of this month, marking a pivotal moment in the HBM battlefield.

He also stated that AI development is only at its first stage, with future growth expected to reach a fifth stage, where AI will interact with humans through intellect and emotion. Kim outlined AI’s key challenges, including power, heat dissipation, and memory bandwidth requirements.

The biggest challenge currently, according to Kim, is power shortages, with data centers expected to need twice the power they do now. Relying solely on renewable energy will not meet this demand, and increased power use will also generate more heat, requiring more efficient heat dissipation solutions.

Thus, SK hynix is working on AI memory that is more energy-efficient, lower in power consumption, and has greater capacity, while also offering solutions tailored to different applications.

Kim then shared the latest progress on HBM3e, noting that SK Hynix was the first supplier to produce 8-layer HBM3e and will begin mass production of 12-layer HBM3e by the end of the month. Additionally, SK Hynix introduced its latest products in DIMM, enterprise SSDs (QLC eSSD), LPDDR5T, LPDDR6, and GDDR7 as well.

Regarding technology development, Kim highlighted that HBM4 will be the first product based on a base die, combining SK hynix’s advanced HBM technology with TSMC’s cutting-edge manufacturing to achieve unparalleled performance. Mass production schedules will be aligned with customer demands.

On a global scale, Kim announced the establishment of a new facility in Yongin, South Korea, with plans to begin mass production in 2027, positioning Yongin as one of the largest and most advanced semiconductor hubs.

Moreover, SK hynix will invest in Indiana, USA, expected to start operations at a new plant in 2028, focusing on advanced HBM packaging.

Eventually, Kim stated that SK hynix will concentrate on AI business, looking to build AI infrastructure with SK Group. This includes integrating power, software, glass substrates, and immersion cooling technology, and working to become a core player in the ecosystem, overcoming challenges with partners to achieve goals in the AI era.

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• [News] SK hynix Secures up to USD 450 Million Funding for Indiana Packaging Facility under CHIPS Act
• [News] SK Hynix President to Join Semicon Taiwan, Bolstering HBM Partnership with TSMC and NVIDIA

The Bank of Canada (BoC) announced a 25 basis point rate cut on September 4, in line with market expectations, marking the BoC’s third consecutive rate cut since June. The BoC noted that CPI growth across its components has returned to historical range, with core inflation  nearing the target range. Although housing and service inflation remains elevated, it has begun to slow down, and there are currently few signs of significant inflationary pressure in Canada.

The BoC is now placing greater emphasis on signs of economic weakness. Recent data indicate that economic growth is slowing, and the unemployment rate has risen due to an increase in labor supply and a slowdown in hiring, which is easing inflationary pressures and introducing downside risks to inflation.

When asked about the pace of future rate cuts, BoC Governor Tiff Macklem stated that if inflationary pressure exceeds expectations, the central bank will maintain its current pace of rate cuts (25 basis points). However, if the economic condition worsens and inflation falls more rapidly, the BoC may accelerate the pace of rate cuts (50 basis points).

According to a report by Reuters, some economists predict that economic weakness could prompt the BoC to implement a 50 basis point rate cut in October or December.

Read more at Datatrack

As Samsung plans to unveil its next-gen flagship smartphone, Galaxy S25 series, in early 2025, more details regarding the product have surfaced. Months ahead of the launch, Samsung is said to abandon the dual-processor strategy and equip the entire series with Qualcomm’s new Snapdragon 8 Gen 4 processor. The latest rumor, however, may be related to the yield issue in its 1b DRAM intended to be used in the Galaxy S25 series.

According to a report by Korean media outlet ZDNet, the tech giant might be facing difficulties in its cutting-edge mobile DRAM, the 1b DRAM (5^th-generation 10nm-class DRAM). Last month, Samsung Electronics’ Mobile eXperience (MX) Division reportedly raised concerns with the Device Solutions (DS) Division about delays in the delivery of 1b-based LPDDR (low-power DRAM) samples.

Samsung has been developing 1b DRAM for a period of time, as the company is said to begin mass production of the 16Gb 1b DDR5 DRAM in May last year, ZDNet notes. Afterwards, Samsung started to develop the 32Gb 1b DRAM in September, targeting the high-performance computing (HPC) market, the report states.

Meanwhile, it has been working on developing 1b LPDDR products for mobile devices, primarily targeting the Galaxy S25 series.

However, recent issues seem to have disrupted these plans, the report suggests. It notes that while the DS Division was expected to deliver 1b LPDDR samples in various capacities, including 12Gb and 16Gb, to the MX Division by last month, they were unable to provide the necessary quantities due to yield problems.

Industry experts cited by the report indicate that semiconductors generally require a yield rate above 80% to support stable and cost-effective mass production and supply. While the exact yield rate of Samsung’s mobile 1b DRAM hasn’t been revealed, it is likely to fall well below the target, which prompts Samsung’s MX Division to reevaluate the schedule and the DRAM adoption plan, the report suggests.

According to a previous report by TheElec, though concerns have been raised regarding its 1b DRAM manufacturing, being ambitious on its HBM development, Samsung targets to tape out HBM4 by the end of this year, while it intends to adopt the 10nm 6th-generation (1c) DRAM to manufacture the memory chip.

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• [News] Samsung Rumored to Abandon Exynos 2500, Equipping Entire S25 Series with Snapdragon

(Photo credit: Samsung)