As per a recent announcement by Nanjing Release, the National Third-Generation Semiconductor Technology Innovation Center (Nanjing) has successfully developed a key technology for the manufacturing of trench-type silicon carbide (SiC) MOSFET chip after four years of independent research. This breakthrough surpasses the performance limitations of planar SiC MOSFET chip, marking the first achievement of its kind in China.

SiC is one of the main representatives of wide bandgap semiconductor materials, characterized by its wide bandgap, high critical breakdown electric field, high electron saturation velocity, and high thermal conductivity. SiC MOSFET primarily comes in two structures: planar and trench, predominantly the former in current SiC MOSFET chip field.

Planar SiC MOS structure features simple process, good cell consistency, and relatively high avalanche energy. However, it faces the issue of JFET effect caused when current is confined to a narrow N-region near the P-body, which increases the on-resistance, and the large parasitic capacitance.

Trench structure refers to embedding the gate into the substrate to form a vertical channel, which allows for increased cell density, elimination of the JFET effect, optimal channel mobility, and significantly reduced on-resistance compared to planar structure. However, the trench process is more complex, with poorer cell consistency and lower avalanche energy.

“The key lies in the process,” explained Huang Runhua, Technical Director at the National Third-Generation Semiconductor Technology Innovation Center (Nanjing).

He noted that SiC is extremely hard, so converting from a planar to a trench structure means “digging a trench” in the material, which must be done with precision to avoid unevenness. During fabrication, the etching process’s precision, etching damage, and residual surface materials critically impact the development and performance of SiC devices.

To address these issues, the Innovation Center organized a core R&D team along with a full support team, and finally established a novel process flow following four years of continuous experimentation with new processes.

They overcame the challenges of precise, stable trench etching and successfully manufactured trench-type SiC MOSFET chip, improving conduction performance by about 30% compared to planar type.

The center is currently developing trench-type SiC MOSFET chip, with the goal of launching trench-type SiC power devices within a year, which are expected to be introduced to applications such as electric vehicle drivetrains, smart grids, photovoltaic energy storage.

What impact does this breakthrough have on our lives and the semiconductor industry? Huang explained, using electric vehicle as an example, that SiC power devices inherently offer power-saving advantages over silicon devices, potentially increasing lifespan by about 5%, and trench structure allows for designs with even lower resistance.

With the same conduction performance, this enables a higher-density chip layout, reducing chip usage costs.

Now, the National Third-Generation Semiconductor Technology Innovation Center (Nanjing) has already started research on SiC superjunction devices. “This structure outperforms the trench-type structure and is currently under development,” Huang Runhua revealed.

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(Photo credit: DRAMeXchange)

Taiwanese Minister of Economic Affairs J.W. Kuo, who was invited to visit Japan, attended a forum on August 30 organized by the Taiwan-Japan Research Institute and delivered a keynote speech. As reported by Kyodo News citing the interview with Kuo, he indicated that TSMC plans to build a third fab in Japan, but with a projected timeline after 2030.

However, Kuo emphasized that the final decision on whether to proceed with the expansion in Japan rests with TSMC, and he refrained from discussing specific site locations.

In addition, in response to Kuo’s comments, the Ministry of Economic Affairs clarified that any details regarding TSMC’s potential third fab should be confirmed with the foundry giant itself.

Reportedly, Kumamoto Prefecture Governor Takashi Kimura visited TSMC’s headquarters on the afternoon of August 26 and held talks with TSMC’s senior executives.

Notably, Takashi Kimura, who took office in April, stated in an report from Bloomberg on May 11th that he would spare no effort to persuade TSMC to establish a third fab in the region, believing that during the preparations for TSMC’s first fab in Kumamoto, the region already possesses better-quality road and water infrastructure and an education system that better supports international school students, which could be advantageous.

TSMC’s fabs in Kikuyo Town, Kumamoto Prefecture (Kumamoto Fab 1) is set to begin mass production in Q4 (October-December), utilizing 28/22nm and 16/12nm process technologies, with a monthly production capacity of 55,000 wafers.

The Kumamoto Fab 2 is scheduled to begin construction at the end of 2024, with the goal of starting operations by the end of 2027, focusing on 6/7nm processes. The combined monthly production capacity of TSMC’s Kumamoto fab 1 and 2 is estimated to exceed 100,000 wafers.

TSMC Chairman C.C. Wei mentioned in June that after the successful operation of the first and second fabs, TSMC would consider building a third fab if it receives the approval of the local residents.

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(Photo credit: TSMC)

AI chip giants NVIDIA and AMD have been under heated competition for a couple of years. NVIDIA, though controls the lion’s share of the market for AI computing solutions, had been challenged by AMD while the latter launched Instinct MI300X GPU in late 2023, claiming the product to be the fastest AI chip in the world, which beats NVIDIA’s H200 GPUs.

However, months after the launch of MI300X, an analysis by Richard’s Research Blog indicates that AMD’s MI300X’s cost is significantly higher than NVIDIA’s H200’s, while H200 outperforms MI300X by over 40% regarding inference production applications, which makes NVIDIA’s high margin justifiable.

AMD’s MI300X: More Transistors, More Memory Capacity, More Advanced Packaging…with a Higher Cost

The analysis further compares the chip specifications between the two best-selling products and explores their margins. NVIDIA’s H200 is implemented using TSMC’s N4 node with 80 billion transistors. On the other hand, AMD’s MI300X is built with 153 billion transistors, featuring TSMC’s 5nm process.

Furthermore, NVIDIA’s H200 features 141GB of HBM3e, while AMD’s MI300X is equipped with 192GB of HBM3. Regarding packaging techniques, while NVIDIA is using TSMC’s CoWoS 2.5D in the H200, AMD’s MI300X has been moved to CoWoS/SoIC 3D with a total of 20 dies/stacks, which significantly increases its complexity.

According to the analysis, under the same process, the number of transistors in the logic compute die and the total die size/total cost are roughly proportional. AMD’s MI300X, equipped with nearly twice the number of transistors compared to NVIDIA’s H200, therefore, is said to cost twice as much of the latter in this respect.

With 36% more memory capacity and much higher packaging complexity, AMD’s MI300X is said to suffer a significantly higher manufacturing cost than NVIDIA’s H200. It is also worth noting that as NVIDIA is currently the dominant HBM user in the market, the company must enjoy the advantage of lower procurement costs, the analysis suggests.

This is the price AMD has to pay for the high specifications of the MI300X, the analysis observes.

NVIDIA’s 80% Margin: High at First Glance, but Actually Justifiable

On the other hand, citing the results of MLPerf tests, the analysis notes that in practical deployment for inference production applications, the H200 outperforms the MI300X by over 40%. This means that if AMD wants to maintain a similar cost/performance ratio (which CSP customers will demand), the MI300X price must be about 30% lower than the H200. The scenario does not take other factors into consideration, including NVIDIA’s familiarity with secondary vendors, the Compute Unified Device Architecture (CUDA), as well as related software.

Therefore, the analysis further suggests that NVIDIA’s 80% gross margin, though might seem to be high at first glance, actually allows room for its competitors to survive. If NVIDIA were to price its products below a 70% margin, its rivals might struggle with negative operating profits.

In addition to achieving better product performance at a lower cost through superior hardware and software technology, NVIDIA excels at non-technical economic factors, including R&D and the scaling of expensive photomasks, which impact operational expenditures (OPEX) and cost distribution as well, while its long-term commitments to its clients, confidence, and time-to-market also play a role, the analysis notes.

Regarding the key takeaways from their latest earnings reports, NVIDIA claims the demand for Hopper remains strong, while Blackwell chips will potentially generate billions of dollars in revenue in the fourth quarter. AMD’s Instinct MI300 series, on the other hand, has emerged as a primary growth driver, as it is expected to generate more than USD 4.5 billion in sales this year.

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(Photo credit: NVIDIA)

Rumors have been circulating that Intel has been working with investment bankers on options to navigate the company through difficulties, which may include selling off its Field Programmable Gate Array (FPGA) unit Altera and halt its investment project in Germany, according to the report by Reuters.

Regarding the status quo of the FPGA market, a report by TechNews states that its applications have been concentrated in small-scale sectors such as communications, defense, and chip prototyping, with Xilinx and Altera dominating the field. As a result, rumors have emerged that Intel might sell its entire Altera division to another chip company looking to expand its product portfolio.

Notably, per industry sources cited in the report from TechNews, it’s further suggested that AMD could be a potential buyer, as it would help the US chip giant expand its FPGA product lineup, which would be more effectively ingrated with its current porfolio.

Altera generated USD 342 million in revenue in the first quarter of 2024, a significant decrease of 58% compared to USD 816 million in the same period last year.

On the other hand, AMD’s Embedded Solutions Division, which includes products acquired from Xilinx in 2022, reported a 46% year-over-year decline in sales to USD 846 million for the first quarter, falling short of Wall Street expectations. Both companies’ recent financial reports have been underwhelming.

In addition to AMD, Marvell, a company specialized in network IC design, has also been reported as a potential buyer for Altera.

Previously revealed in a report by Bloomberg on August 29 citing sources, Intel is said to be considering several potential strategies, including spinning off its product design and foundry businesses, canceling some of its regional facility construction plans, or pursuing mergers. These options are expected to be discussed at the board meeting scheduled for September.

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• [News] Intel Reportedly Mulls to Sell FPGA Unit Altera and Freeze USD 32 Billion German Project amid Crisis
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(Photo credit: AMD)

Japanese NAND Flash giant Kioxia is striving for a V-shaped recovery in its performance. According to a report from Japanese news outlet 47news, benefiting from the quick rebound in the semiconductor market, Kioxia’s revenue this fiscal year is reportedly set to reach an all-time high, with operating profit nearing a historic second-highest level.

It is reported that Kioxia’s revenue for the fiscal year 2024 (April 2024 – March 2025) is estimated to reach JPY 1.6 trillion, setting a new historical high.

This is expected to be accompanied by an operating profit of around JPY 300 billion. Kioxia’s strong performance this fiscal year is in contrast with the previous fiscal year (April 2023 – March 2024), which recorded a loss of JPY 252.7 billion, the largest in its history.

The report also suggests that Kioxia is forecasted to maintain similar strong performance in the next fiscal year 2025 (April 2025 – March 2026).

The company’s highest annual revenue record stands at JPY 1.5265 trillion for the fiscal year 2021, with a peak operating profit of JPY 456.8 billion in the fiscal year 2017.

Kioxia was formerly known as Toshiba Memory. It became an independent entity spun off from Toshiba in June 2018 and rebranded as Kioxia in October 2019.

Recently, Japanese news outlet Nikkei reported that Kioxia submitted its listing application to the Tokyo Stock Exchange on August 23, with the goal of going public as soon as October.

Reportedly, Kioxia’s valuation is expected to exceed JPY 1.5 trillion (roughly USD 10.3 billion). The deal is anticipated to surpass the JPY 420 billion raised by chip equipment maker Kokusai Electric during its 2023 IPO, which was the largest of that year.

It is also expected to exceed the projected listing of Tokyo Metro in October, estimated at JPY 640 billion to 700 billion.

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(Photo credit: Kioxia)