As semiconductor manufacturing enters the Angstrom Era, there have been significant adjustments in architecture and circuit design. To free up more surface area on chips, moving power delivery to the backside has become a mainstream consensus, making the Backside Power Delivery Network (BSPDN) the premier solution in advanced manufacturing.

According to a report from Commercial Times, regarding BSPDN, leading companies such as TSMC, Intel, and imec (Belgian Microelectronics Research Center) have proposed different approaches focusing on wafer thinning, atomic layer deposition (ALD) inspection, and wafer regeneration solutions, with mass production starting from 2026, benefiting supply chains.

Among them, TSMC’s Super Power Rail is considered direct and effective, albeit complex and expensive to implement. To reflect its value, TSMC has adjusted its pricing strategy. According to the report, the foundry leader has successfully raised prices for advanced processes, with further increases slated for January 1 next year, particularly targeting the 3/5-nanometer AI product lines with adjustments ranging from 5% to 10%.

Industry sources cited by the same report point out that there are several technological breakthroughs in backside power delivery. One critical aspect involves polishing the wafer backside to a thickness close enough for transistor contact. However, this process significantly compromises the wafer’s rigidity. Therefore, after front-side polishing, it’s essential to bond a carrier wafer to support the backside manufacturing process.

Additionally, technologies like nano Through-Silicon Vias (nTSV) require more equipment for ensuring uniform copper metal deposition within nano-scale holes.

Therefore, leading companies have proposed different approaches focusing on wafer thinning, atomic layer deposition (ALD) inspection, and wafer regeneration solutions. This development is benefiting related supply chain entities such as Kinik Company, Skytech, and Phoenix Silicon International Corporation.

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(Photo credit: TSMC)

According to TrendForce’s latest memory spot price trend report, the spot price of DRAM has finally seen a slight raise as supply for DDR4 and DDR5 tightens. Samsung has allocated more of its 1alpha nm production capacity to the manufacturing of HBM products, which leads to DDR5’s price increase. As for NAND flash, transactions within the spot market remain sluggish. Details are as follows:

DRAM Spot Price:

In the spot market, there has been a slight decrease in the supply of used DDR4 chips that were originally stripped from decommissioned modules. Moreover, spot prices of DDR4 chips had already dropped to a low of US$0.9 at the end of 2023, so there has been a modest rebound recently. However, there has not been a significant rebound in the demand for consumer electronics. As a result, the price increase for DDR4 chips is expected to be limited. As for DDR5 products, the supply has tightened primarily because Samsung has allocated more of its 1alpha nm production capacity to the manufacturing of HBM products. Additionally, there have been special cases of buyers requesting quotes for DDR5 products recently. Consequently, prices of DDR5 products have registered a slight rise. The average spot price of mainstream chips (i.e., DDR4 1Gx8 2666MT/s) has risen by 1.07% from US$1.875 last week to US$1.895 this week.

NAND Flash Spot Price:

Transactions within the spot market are currently at a sluggish stage, and the occasional appearance of rush orders are unable to provide a support for price increases. It is worth noting that spot traders and several module houses are fighting for orders by cutting down their prices sporadically due to pressure from inventory and funds. On the whole, module houses are still actively seeking for buyer orders in the hope of seeing a need of inventory replenishment during the traditional peak season that is 3Q24. Spots of 512Gb wafers have dropped by 0.33% this week, arriving at US$3.291.

While NVIDIA is likely to face accusations from the French antitrust regulators, the Non-NVIDIA Alliance like the UALink (Ultra Accelerator Link) Alliance and the UXL Foundation are reportedly launching a counterattack, significantly increasing their efforts in developing specialized ASICs.

According to a report from Commercial Times, relevant semiconductor intellectual property (IP) is expected to be widely adopted. The sources cited by the report point out that Taiwanese manufacturers, benefiting from their leading position in wafer foundry and comprehensive ASIC and IP layout, are poised to capitalize on the rise of the Non-NVIDIA Alliance.

The report further cites sources, indicating that major Taiwanese ASIC manufacturers such as Global Unichip, Faraday Technology, and Progate Group Corporation (PGC), along with silicon IP companies M31 Technology Corporation, eMemory, and the Egis Technology Group, are actively expanding in this field.

In order to challenge NVIDIA’s dominance in the market, UALink (Ultra Accelerator Link) Alliance, led by tech giants such Intel and AMD, was formed in May. The alliance aims to establish a new standard for AI accelerator links, aiming to challenge NVIDIA’s  NVLink.

Furthermore, the UXL Foundation’s Open Source Software Project, supported by tech giants Qualcomm, Google, and Intel, is said to be looking to rival NVIDIA’s CUDA software. By providing alternative software solutions, it aims to diminsh NVIDIA’s dominance in the AI field.

Semiconductor industry sources cited in the same report also note that CSPs are accelerating the development of their own chips, with Taiwanese manufacturers actively entering the market.

Although Broadcom and Marvell currently offer diversified design services, Taiwanese manufacturers have an advantage due to the tightly-knit semiconductor supply chain. This enables complete solutions for both chip manufacturing and packaging within Taiwan, giving them a strategic edge over competitors by being close to both the market and factories, thereby enhancing their position in the ASIC sector.

Global Unichip and PGC leverage TSMC as a strong ally. Reportedly, Global Unichip holds AI-related ASIC orders from Microsoft and is gradually finalizing collaborations with major South Korean companies, with business operations expected to improve in the second half of the year.

On the other hand, Faraday Technology closely collaborates with Intel, developing SoCs using Intel’s A18 process. Meanwhile, industry sources cited by the report suggest that Intel’s Gaudi series AI chips might seek collaboration opportunities beyond just working with Alchip.

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(Photo credit: Shutterstock)

According to a report from Commercial Times, Arthur Chiao, Chairman of Winbond, stated that this upward market cycle for the memory sector has arrived on time. Reportedly, customers are not worried about shortages, and all products made by Winbond will sell well all year round, boosting the momentum in 2025.

Looking at Winbond’s recent revenue trend, the company’s performance has risen in the second quarter, further hinting that the upward market cycle has arrived on time. Chao anticipates that this upward cycle could last for two years, making 2025 a good year throughout, with a possible downturn in 2026.

Considering Winbond’s NOR Flash, which has held the largest global market share since 2020, Chiao noted that this product is widely used in automotive, communication, telecommunications, wearable devices, and other technological applications. Overall, its sales recovery also represents a revival of the electronics market.

Regarding individual industries, as per the same report, Winbond expects the PC end market to grow by 5% to 10% in 2024. The mobile phone market, which has been in decline for three years, is also rebounding from its trough, with an estimated single-digit percentage growth. Consumer products, the first sector to undergo inventory adjustments, are also the fastest to recover. Networking and communications, driven by the growing application of Wi-Fi 7, is also optimistic in the second half of the year.

Winbond is also implementing the NCNT (Non-Taiwan, Non-China) strategy. Arthur Chiao emphasized that global trends are irreversible, and the company is starting to make early preparations in response to customer demands. Winbond’s General Manager, Pei-Ming Chen, added that the company will outsource packaging and testing to a partner factory in Malaysia and will first conduct product verification work. Although costs will rise, customers have indicated that it is acceptable.

Chiao further stated that in response to the AI trend, Winbond has adjusted its strategy and business organization. The company is transitioning from a component supplier to a service-oriented manufacturer and have established a dedicated business unit for customized memory solutions (CMS).

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(Photo credit: Winbond)

As artificial intelligence (AI) technology enjoys rapid advances, the demand for AI chips is skyrocketing, driving continuous improvements in advanced packaging and HBM (High Bandwidth Memory) technology, which is expected to benefit the silicon wafer industry.

Recently, Doris Hsu, the Chairperson of GlobalWafers, revealed that HBM memory chips required by AI, such as HBM3 and the upcoming HBM4, need to be stacked on dies, with the number of layers increasing from 12 to 16. Additionally, a layer of base wafer is required underneath the structure, which adds to the consumption of silicon wafers.

Previously, it’s reported that there is a severe global shortage of HBM amid the AI boom, and original manufacturers’ HBM production capacity for this year and next already sold out. They are continuously revving up capital investment and expanding HBM production. According to industry insiders, compared to memory technologies of the same capacity and process like DDR5, the size of wafer for HBM chip has increased by 35-45%. Meanwhile, the complexity of HBM manufacturing processes leads to a yield rate that is 20-30% lower than DDR5, while lower yield rate means that fewer qualified chips can be produced from the same wafer area. These two factors imply that more silicon wafers are needed to meet HBM production demands.

Apart from memory, innovations in advanced packaging technology also conduces to silicon wafer. Hsu mentioned that more polished wafers are required for advanced packaging than before in that packaging has become three-dimensional, and the structure and processes have also changed, which means that some packaging may require twice as many wafers as before. With the releasing of  advanced packaging capacity next year, the number of wafers needed will be even more significant.

As an advanced packaging technology, CoWoS (Chip on Wafer on Substrate) is in vogue currently, with demand overbalancing supply.

As per TrendForce’s survey, NVIDIA’s B series, including GB200, B100, and B200, will consume more CoWoS capacity. TSMC is also increasing its annual CoWoS capacity for 2024, with monthly capacity expected to approach 40k by the end of this year, an over 150% increase compared to 2023. The planned total capacity for 2025 could nearly double, and the demand from NVIDIA is expected to account for more than half.

Industry insiders pointed out that with the development of advanced semiconductor processes in the past, die size reduced and brought down the consumption of wafer. Now, driven by AI, the three-dimensionality of packaging leads to an increase in wafer usage, thereby facilitating the development of the silicon wafer industry. However, it is important to note that while silicon wafer is experiencing a boon, the development of HBM and advanced packaging technologies imposes higher requirements on the quality, flatness, and purity. This will also prompt silicon wafer manufacturers to make corresponding adjustments to cope with the AI trend.

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