According to a report from Korean media outlet ZDNet Korea, the yield rate for Samsung Electronics’ latest Exynos 2500 processor has improved to slightly below 20% from single digits in the first quarter. However, the current yield rate is still said to be falling short of mass production standards. It remains uncertain whether it can be used in the flagship Galaxy S25 series smartphones in the future.

The report further indicates that this yield rate is still insufficient for mass production, which typically requires yields to be increased to over 60%. Therefore, Samsung Electronics’ System LSI department reportedly plans to work on improving the yield rate of the Exynos 2500 processor in the second half of this year.

The report states that it is still uncertain whether the Exynos 2500 processor can be used in the future Galaxy S25 series flagship smartphones. Since there is still considerable time before the official launch of the Galaxy S25 series, Samsung hopes to improve the yield rate of the Exynos 2500 processor to 60% by October this year.

On the other hand, TSMC is overwhelmed with 3nm orders, with major companies like Apple, NVIDIA, AMD, Qualcomm, Intel, and MediaTek all utilizing TSMC’s 3nm process. Per a report from TechNews, during TSMC’s technology forum on May 23, the 3nm production capacity this year has more than tripled compared to last year, but this is actually still not enough, so efforts are still being made to meet customer demand.

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• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] Samsung Reportedly to Challenge Apple/TSMC with 3nm Exynos W1000

(Photo credit: Samsung)

According to a report by the Economic Daily News, TSMC has secured another AI business opportunity. Following its exclusive contract manufacturing of AI chips for tech giants such as NVIDIA and AMD, TSMC, in collaboration with its subsidiary, the ASIC design service provider Global Unichip Corporation (GUC), has reportedly made significant progress in producing essential peripheral components for AI servers, specifically high-bandwidth memory (HBM). Together, they have secured a major order for the foundational base die chips of next-generation HBM4.

TSMC and GUC typically do not comment on order details. SK Hynix, on the other hand,  has clarified in a press release to Bloomberg that it has not signed a contract with GUC for its next-generation AI memory chips, according to the Economic Daily News.

Industry sources cited by the report point out that the strong demand for AI is not only making high-performance computing (HPC) related chips highly sought after, but also driving robust demand for HBM, creating new market opportunities. This surge in demand has attracted major memory manufacturers such as SK Hynix, Samsung, and Micron to actively invest. Under the influence of AI engines, the current production capacity for HBM3 and HBM3e is in a state of supply shortage.

As AI chip manufacturing advances to the 3nm generation next year, the existing HBM3 and HBM3e, limited by capacity and speed constraints, may prevent the new generation of AI chips from reaching their maximum computational power. Consequently, the three major memory manufacturers are unanimously increasing their capital expenditures and starting to invest in the development of next-generation HBM4 products, aiming for mass production by the end of 2025 and large-scale shipments by 2026.

While memory manufacturers are delving into the research and development of next-generation HBM4, the semiconductor standardization organization JEDEC Solid State Technology Association is also busy establishing new standards related to HBM4. It’s also rumored that JEDEC will relax the stacking height limit for HBM4 to 775 micrometers, hinting that the previously required advanced packaging technology using hybrid bonding can be postponed until the next generation of HBM specifications.

Industry sources cited by the report also suggest that the most significant change in HBM4, besides increasing the stacking height to 16 layers of DRAM, will be the addition of a logic IC at the base to enhance bandwidth transmission speed. This logic IC, known as the base die, is expected to be the major innovation in the new generation of HBM4 and possibly a reason for JEDEC’s relaxation of the stacking height limitation.

On the other hand, SK Hynix has announced its collaboration with TSMC to advance HBM4 and capture opportunities in advanced packaging. Industry sources also indicate that GUC has successfully secured the critical design order for SK Hynix’s HBM4 base die.

The design is expected to be finalized as early as next year, with production to be carried out using TSMC’s 12nm and 5nm processes, depending on whether high performance or low power consumption is prioritized.

Reportedly, it’s suggested that SK Hynix’s decision to entrust the base die chip orders to GUC and TSMC is primarily because TSMC currently dominates over 90% of the CoWoS advanced packaging market used in HPC chips.

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• [News] SK Hynix Disclosed Details Regarding HBM4e, Reportedly Integrating Computing and Caching Functionalities
• [News] SK Hynix Partners with TSMC to Strengthen HBM Technological Leadership

(Photo credit: TSMC)

On June 18th, Belgium’s microelectronics research center IMEC showcased the first CMOS CFET device featuring stacked bottom and top source/drain contacts at the 2024 IEEE VLSI Technology and Circuits Symposium (2024 VLSI). Although the results were achieved using front-side lithography techniques for both contacts, imec also demonstrated the feasibility of transferring the bottom contacts to the back side of the wafer, which potentially increases the survival rate of top devices from 11% to 79%.

IMEC explained that their logic technology roadmap envisions the introduction of Complementary Field-Effect Transistor (CFET) technology into device architectures at the A7 node. Paired with advanced wiring technologies, CFET is expected to reduce the standard cell height from 5T to 4T or even lower without sacrificing performance. Among the different approaches to integrating vertically stacked nMOS and pMOS structures, monolithic integration is considered the least disruptive compared to existing nanosheet process flows.

At VLSI Symposium 2024, IMEC demonstrated for the first time a functional monolithic CMOS CFET device with both top and bottom contacts. The device features a gate length of 18nm, a gate pitch of 60nm, and a vertical distance of 50nm between the n-type and p-type. The process flow IMEC’s proposed includes two CFET-specific modules: Middle Dielectric Isolation (MDI) and stacked bottom and top contacts.

MDI is a module pioneered by IMEC to isolate the top and bottom gates and to differentiate threshold voltage settings between n-type and p-type devices. Based on modifications to the “active” multilayer Si/SiGe stack in CFET, MDI module allows for the co-integration of internal spacers—a feature unique to nanosheets that isolates the gate from the source/drain.

“We obtained the best results in terms of process control with an MDI-first approach, i.e., before source/drain recess – the step where nanosheets and MDI are ‘cleaved’ to gain access to the channel sidewalls and start source/drain epi. An innovative source/drain recess etch with ‘in-situ capping’ enables MDI-first by protecting the gate hardmask/gate spacer during the source/drain recess.” stated Naoto Horiguchi, IMEC’s CMOS device technology director, as per a report from IMEC.

The second critical module is the formation of stacked source/drain bottom and top contacts, vertically separated by dielectric isolation. Key steps involve bottom contact metal filling and etching, followed by dielectric filling and etching—all completed within the confined space of the MDI stack.

Naoto Horiguchi noted that developing bottom contacts from the front side encountered many challenges, which potentially impacts bottom contact resistance and limits the process window for top devices. At VLSI 2024, IMEC indicated that despite additional processes like wafer bonding and thinning, this design is proved feasible, making the backside bottom contact structure an attractive option for the industry. Currently, research is underway to determine the optimal contact wiring method.

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• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: IMEC)

SK keyfoundry, a subsidiary of memory giant SK hynix, has achieved notable progress in the development of Gallium Nitride (GaN) power semiconductors. According to the latest report by Business Korea, the foundry would begin producing power semiconductors for Tesla in the second half of 2024.

According to the report, SK keyfoundry announced in early June that it has achieved the primary device characteristics of a 650V GaN High Electron Mobility Transistor (HEMT), which surpasses traditional silicon-based semiconductors in both efficiency and durability. This advancement aligns with SK keyfoundry’s plan to finalize the development of GaN power semiconductors by the end of this year.

It is worth noting that TSMC has also entered the GaN market a few years ago, as it provides GaN process for manufacturing 100/650V discrete GaN power devices for customers. For instance, in 2020, the world’s largest foundry has announced to collaborate with STMicroelectronics. According to its press release, ST’s GaN products will be manufactured using TSMC’s leading GaN process technology, including applications relating to automotive converters and chargers for hybrid and electric vehicles.

Regarding the development of SK keyfoundry, Business Korea noted that the company established an official team in 2022 to focus on the development of GaN technologies. Citing industry sources on June 20^th, the report stated that SK keyfoundry will reportedly begin producing power semiconductors for Tesla in the second half of this year.

Moreover, it also mulls to broaden its business scope, entering markets like fast-charging adapters, data centers, and energy storage systems afterwards. Starting in November, the company plans to manufacture power management chips (PMIC) at its 8-inch wafer fab in Cheongju.

Though foundries have not significantly contributed to SK hynix’s revenue so far, the development of power semiconductors could boost overall foundry sales. According to the report, SK keyfoundry also provides contract manufacturing for non-memory semiconductors such as Display Driver ICs (DDI) and Microcontroller Units (MCU), further diversifying its product lineup.

In the current landscape of the new energy market, third-generation semiconductors such as SiC and GaN have gained significant traction. SiC (Silicon Carbide) and GaN could offer significant benefits over traditional silicon.

To elaborate, semiconductor materials have the so-called “bandgap,” an energy range in a solid where no electrons can exist. According to German chipmaker Infineon, GaN has a bandgap of 3.4 eV, compared to silicon’s 1.12 eV bandgap. The wider bandgap of GaN allows it to sustain higher voltages and temperatures than silicon. While SiC dominates the high-power domain, GaN excels at lower power levels, offering lower conduction losses.

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• [News] Infineon in GaN and SiC Expansion Drive Advancements in the New Energy Market

(Photo credit: SK keyfoundry)

According to a report from CNA, Taiwanese semiconductor testing and packaging giant ASE announced on June 21st that it will collaborate with Hung Ching Development & Construction Corporation to jointly build the K28 plant in Kaohsiung. Scheduled for completion in Q4 2026, the facility will reportedly focus on advanced packaging and final testing in order to meet the high-performance computing and cooling demands of AI chips.

ASE’s CFO Joseph Tung stated that ASE Semiconductor is planning for operational growth at its Kaohsiung facilities. To meet the demand for advanced packaging processes, high-performance computing for AI chips and cooling, the company is developing land in Dashe, Kaohsiung in two phases. The first phase, K27 plant, was completed and moved-in in 2023, while the K28 plant, the second phase, aims to be completed by Q4 2026.

As reported by CNA citing sources, ASE Kaohsiung Plant contributes approximately 20% to ASE Technology Holding Co., Ltd.’s total revenue. The plant specializes in providing services such as packaging, wafer bumping, probe testing, materials, and final testing. It has also developed several smart factories focusing on advanced processes, including Fan-out packaging, System-in-Package (SiP), wafer bumping, and Flip Chip packaging.

These technologies are primarily used in automotive, medical, IoT, high-speed computing, artificial intelligence, and application processor fields.

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• [News] Following TSMC, ASE Reportedly Plans to Establish Plant in Kumamoto
• [News] ASE Expands Production at Kaohsiung Plant, Focusing on Advanced Packaging for AI Chips