According to a report by the Korean media outlet The Chosun Daily on June 16th, Samsung’s “Galaxy Tab S10” series tablets will be equipped with MediaTek’s Dimensity 9300+ application processor (AP) from Taiwan, marking the first instance of MediaTek’s AP being adopted by Samsung’s flagship tablet.

The report highlights that MediaTek’s APs have primarily been used in Samsung’s mid-to-low-end smartphones. The decision to use MediaTek’s AP in the Galaxy Tab S10 series, instead of Qualcomm’s or Samsung’s own APs, is a significant shift for Samsung.

The sources cited in the report believe that Samsung’s move is a butterfly effect caused by TSMC’s price hikes. TSMC’s price increases have potentially led to a rise in the cost of Qualcomm’s Snapdragon chips, which are manufactured by TSMC. After price negotiations, Samsung’s Mobile Communications Business (MX) decided to equip the Snapdragon 8 Gen 3 chips only in the Galaxy Tab S10 Ultra series, while using MediaTek’s Dimensity chips in the Plus and base models.

The same report further indicates that from Samsung’s perspective, choosing Dimensity to reduce costs and diversify the supply chain is a sensible decision. However, for Samsung’s foundry division which manufactures Exynos, this development is somehow unwelcome. While Exynos used to have price advantages over Snapdragon in supplying Samsung’s flagship products, the use of Dimensity jeopardizes Exynos’ competitive edge in its bargaining power for future flagship product pricing negotiations.

Samsung Electronics’ upcoming AP, the “Exynos 2500,” set for release next year, will also face similar challenges. With TSMC recently rumored to increase price for its 3nm process, costs for Qualcomm’s Snapdragon 8 Gen 4, slated for release in October, are expected to sharply increase. Industry source cited by the report further suggests the cost of this chip could rise from over USD 200 in the previous generation to more than USD 250.

TSMC Chairman C.C. Wei recently stated that, almost all companies interested in AI-related demand are willing to work with TSMC. From the yield rates obtained by customers, TSMC offers the best cost-effectiveness solutions, hence there is room for price increases. Per a report from Liberty Times, the wafer order prices for TSMC in 2025 are expected to be finalized in September and October this year.

Read more

• [News] Samsung Reportedly to Challenge Apple/TSMC with 3nm Exynos W1000
• [News] MediaTek Announces 4nm Dimensity 7300 Series Chips, Supporting Foldable Devices

(Photo credit: MediaTek)

In 2023, Samsung disclosed plans to launch its advanced three-dimensional (3D) chip packaging technology, which would be able to integrate memory and processors needed for high-performance chips, in much smaller sizes. Now, at the Samsung Foundry Forum in San Jose taken place in June, the tech giant made it public that it would introduce 3D packaging services for HBM within this year, according to the latest report by The Korea Economic Daily.

For now, HBM chips are predominantly packaged with 2.5D technology. Citing industry sources as well as personnel from Samsung, the company’s 3D chip packaging technology is expected to hit the market for HBM4, the sixth generation of the HBM family.

Samsung’s announcement regarding its 3D HBM packaing roadmap has been made after NVIDIA CEO Jensen Huang revealed Rubin at COMPUTEX 2024, the company’s upcoming architecture of its AI platform after Blackwell. The Rubin GPU will reportedly feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, targeting to be released in 2026.

Currently, Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs, while SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D, on the other hand, entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

The Korea Economic Daily noted that unlike 2.5D technology, under which HBM chips are horizontally connected with a GPU on a silicon interposer, by stacking HBM chips vertically on top of a GPU, 3D packaging could further accelerate data learning and inference processing, and thus does not require a silicon interposer, a thin substrate that sits between chips to allow them to communicate and work together.

It is also understood that Samsung plans to offer 3D HBM packaging on a turnkey basis, according to the Korea Economic Daily. To achieve this, its advanced packaging team will vertically interconnect HBM chips produced by its memory business division, with GPUs assembled for fabless companies by its foundry unit, the report noted.

Regarding Samsung’s long-time rival, TSMC, the company’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and HBM stacks side by side on one interposer. TSMC also made similar announcement in May, reportedly utilizing 12nm and 5nm process nodes in manufacturing HBM4, according to a report by AnandTech.

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• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process
• [News] Samsung Accelerates 3D Packaging with Hybrid Bonding Production Line in Korean Advanced Packaging Hub

(Photo credit: Samsung)

Taiwan’s semiconductor giant, TSMC, faces overwhelming demand for its 3nm technology, with major clients like Apple and NVIDIA fully allocate its production capacity.

According to a report from Commercial Times, orders are expected to be filled through 2026. Reportedly, TSMC is planning to raise its 3nm prices by over 5%, and advanced packaging prices are anticipated to increase by approximately 10% to 20% next year.

The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A. As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.

N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.

Source: TSMC

Per the industry sources cited by the same report, TSMC’s Zhunan advanced packaging plant (AP6), operational for a year now, has become Taiwan’s largest CoWoS base with the equipment moved into its AP6C plant. In the third quarter, CoWoS monthly production capacity is expected to double from 17,000 to 33,000 wafers.

Industry sources cited by the report further suggests that while AI accelerators do not use the most cutting-edge manufacturing processes, they rely heavily on advanced packaging technology. The ability of global semiconductor companies to secure more advanced packaging capacity from TSMC will determine their market penetration and control.

TSMC’s advanced packaging capacity is scarce, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. Broadcom, Amazon, and Marvell have also expressed strong interest in using advanced packaging processes. With gross margins close to 80%, NVIDIA is said to agree to price increases to secure more advanced packaging capacity, thereby distancing itself from competitors.

Previously, NVIDIA CEO Jensen Huang emphasized that TSMC is not just manufacturing wafers but also handling numerous supply chain issues. He also agreed that the current pricing is too low and would support TSMC’s price increase actions.

The industry sources cited by Commercial Times have indicated that TSMC plans to add CoWoS-related equipment by the third quarter and has requested equipment manufacturers to dispatch more engineers to fully staff its Longtan AP3, Zhunan AP6, and Central Taiwan Science Park AP5 plants.

In addition to Zhunan’s AP6C, the Central Taiwan Science Park plant, which originally only handled the latter stages of oS, will also gradually transition to CoW processes. Meanwhile, the Chiayi site is in the land preparation stage and is expected to progress faster than Tongluo.

Reportedly, industry sources further reveal that the prices for advanced process nodes such as 3nm and 5nm will also be adjusted. Particularly, strong demand for 3nm orders in the second half of the year is expected to drive utilization rates to near full capacity, extending through 2025. The 5nm process is experiencing similar demand dynamics, driven by AI needs.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)

One major challenge for China’s IC design industry is the lack of advanced domestic Electronic Design Automation (EDA) tools. Due to US export controls, suppliers like Cadence and Synopsys are unable to provide chip design software to China. Additionally, the absence of domestic EDA tools capable of operating on Chinese-made CPUs adds further pressure.

However, according to a report from TechNews, there are signs of change. Chinese company X-Epic has introduced the first EDA software capable of running on domestically produced processors in China, potentially breaking through existing limitations.

As per a report from Tom’s Hardware, at the Kunpeng Developer Day on April 25, 2024, X-Epic presented the latest developments in China’s domestic chip design software EDA.

This platform is compatible with Huawei’s Kunpeng server processors based on Armv8 architecture and also supports Phytium’s Phytium processors based on SPARCv9 architecture. This represents a significant advancement for China’s semiconductor design industry, enabling domestic chip designers to conduct chip design and simulation using local software only.

X-Epic stated that they provide a comprehensive suite of chip design software EDA tools covering various aspects such as digital chip verification, hardware simulation, system debugging, and cloud-based verification. Extensive adaptation and optimization have already been completed, including adaptation to compilation environments, C++/ASM compilation, cmake compilation scripts, and third-party function libraries. The focus of application lies particularly on Huawei’s Kunpeng platform.

X-Epic has indicated that, through tools like GalaxSim and GalaxFV, X-Epic achieved 2 to 3 times performance enhancements in multiple customer test cases on Huawei’s high-performance Kunpeng server clusters compared to non-optimized software. These enhanced capabilities have notably reduced simulation testing times and improved efficiency in system-level chip simulation verification. However, there is currently no information available regarding test results for Phytium’s Phytium processors.

Overall, this collaboration not only strengthens Huawei’s Kunpeng ecosystem but also provides a comprehensive chip design software EDA solution for China’s domestic semiconductor industry.

Read more

• [News] Huawei’s HarmonyOS Project Ready to Hit the Road with Increasing Participation from Chinese Enterprises
• [Report Highlights] China’s EDA Industry Enters a Period of Consolidation amidst Rapid Growth

(Photo credit: X-Epic)

Due to the EU’s announcement of increased tariffs on Chinese-made electric vehicles, Tesla has announced that it will raise the price of the Model 3 in the European market starting in July, though the extent of the price increase has not been specified.

According to a report from CNBC, Tesla CEO Elon Musk stated on June 13th that the Model 3 price in the European market will be adjusted starting July 1st due to the EU tariffs, without revealing the specific increase.

Per a report from Reuters, the European Commission has announced that, starting July 4th, it will impose tariffs ranging from 17.4% to 38.1% on electric vehicles imported from China. The tariff rates will vary depending on the extent of government subsidies received by each automaker. This measure aims to prevent Chinese manufacturers benefiting from government subsidies from undercutting the market with cheap electric vehicles, thereby harming the EU automotive industry.

It is unclear how much of a tariff will be imposed on Tesla’s Chinese-made electric vehicles. The European Commission stated that Tesla will be subject to an individually calculated tariff rate. Whether Tesla cooperates with the EU authorities’ anti-subsidy investigation will also influence the final tariff rate applied.

Although the EU has decided to impose high tariffs on Chinese electric vehicles, there are still differing opinions among various parties. The German government and automotive industry have reacted most strongly, fearing it could ignite a China-EU trade war.

Per a report from Xinhua citing sources, Tesla’s Shanghai plant is the U.S. car manufacturer’s first gigafactory outside the US, delivered 947,000 vehicles in 2023.

As per a previous report from Barron’s, German Transport Minister Volker Wissing stated that, “The European Commission’s punitive tariffs hit German companies and their top products. Cars must become cheaper through more competition, open markets and significantly better business conditions in the EU, not through trade war and market isolation.”

Read more

• [News] EU Plans to Impose Tariffs as High as 38.1% on Chinese Electric Vehicles Amid Trade War
• [News] TSMC Reportedly Commences Production of Tesla’s Next-Generation Dojo Chips, Anticipates 40x Increase in Computing Power in 3 Years

(Photo credit: Tesla)