While 2nm advanced semiconductor chips are yet to enter mass production, the battle for equipment among semiconductor foundries is already in full swing.

TSMC, Samsung, and Rapidus Make Their Moves

To ensure the smooth deployment of 2nm process technology, TSMC, Samsung, and Rapidus have all embarked on pursuits in the upstream equipment sector.

TSMC, on September 12th, announced its intention to acquire a 10% stake in IMS Nanofabrication, a subsidiary of Intel, for no more than $432.8 million. IMS specializes in the development and production of electron beam lithography machines, widely used in semiconductor manufacturing, optical component production, MEMS manufacturing, and more. Industry experts believe that TSMC’s acquisition of IMS will ensure the development of critical equipment technology and meet the supply requirements for the commercialization of 2nm.

On the other hand, Samsung previously acquired a 3% stake in ASML, still holding approximately 0.7% of ASML shares. Additionally, Samsung’s collaboration with ASML continues to deepen. Reports suggest that Samsung is preparing to secure production of the next-generation High-NA EUV lithography machine, with the prototype expected to be unveiled later this year and commercial availability in the following year.

As for the semiconductor newcomer, Rapidus, obtaining ASML’s support is essential, given that EUV is a vital technology for mass-producing chips below 5-7nm. The latest reports from Japanese media indicate that ASML will establish a technical support base in Hokkaido, Japan, in 2024 and dispatch about 50 engineers to assist in setting up EUV lithography equipment in Rapidus’ 2nm chip factory’s pilot production line, offering assistance in commissioning, maintenance, and inspection.

The development of the major manufacturers in 2nm will be revealed in 2025

Leading traditional semiconductor foundries TSMC and Samsung, along with the emerging player Rapidus, are all actively positioning themselves in the 2nm chip landscape. So, how are these three companies progressing?

TSMC is targeting the production of N2 technology by 2025. Reports from June indicated that TSMC is fully committed, initiating preliminary preparations for the trial production of 2nm chips. In July, the TSMC supply chain revealed that TSMC had informed equipment suppliers to begin deliveries of 2nm-related machinery starting in the third quarter of the following year. In September, media reports revealed that TSMC had formed a dedicated 2nm task force, aiming to achieve risk production next year and commence mass production by 2025.

In June, Samsung announced its latest foundry technology innovations and business strategies, unveiling detailed plans and performance levels for 2nm process mass production. They plan to apply the 2nm process to mobile applications by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

According to Rapidus’ plan, trial production of 2nm chips is set to begin in 2025, with mass production slated for 2027. In July, Rapidus President Atsuyoshi Koike stated that operating a trial production line in 2025 and commencing mass production in 2027 is an ambitious goal, but progress is on track. He noted that once the company’s 2nm process products go into mass production, their unit price will be ten times that of current Japanese-produced logic semiconductors.

With this timeline, it appears that the 2nm chips from these three semiconductor giants will first make their debut in 2025. At that time, the competition for advanced 2nm processes is expected to become even more intense.

(Photo credit: TSMC)

According to Taiwan’s Media TechNews, Taiwan Semiconductor Manufacturing Company (TSMC) is actively building its 2-nanometer (2nm) fab, with significant investments in the northern, central, and southern regions of Taiwan. These investments include the Baoshan fab in Hsinchu, the Central Taiwan Science Park fab, and the Nanzi fab in Kaohsiung. However, the latest supply chain reports suggest that the construction progress of the Baoshan fab is slowing down, potentially affecting the original production schedule. Industry sources speculate that mass production may be delayed until 2026.

In response to these rumors, TSMC stated that the factory construction is currently progressing according to the planned schedule.

TSMC had originally planned to construct Fab 20 at the Baoshan Phase 2 site, with a plan for four 12-inch wafer fabs (P1~P4). Risk Production was scheduled for the second half of 2024, followed by mass production in 2025. Currently, the latest progress indicates that the Hsinchu Science Park Administration has initiated public works for the expansion of the Baoshan Phase 2 project, including infrastructure like surrounding roads and wastewater facilities, and is concurrently handing over the land for TSMC to begin construction.

However, based on supply chain reports, the Baoshan fab construction project is slowing down due to subdued semiconductor demand and uncertainties customer adoption. As a result, the originally scheduled mass production in the second half of 2025 may likely be delayed until 2026.

As for the Kaohsiung fab, it is concurrently starting its 2nm construction, with equipment installation operations originally scheduled to begin just one month after the Baoshan fab. It remains uncertain whether the slowdown in the Baoshan fab construction will have a synchronous impact on the Kaohsiung fab. As for the Taichung fab, it has received approval from the Taichung City government, but construction is expected to commence next year. Some media reports suggest that the Central Taiwan Science Park fab may potentially advance to produce at 1.4nm or even 1nm semiconductor nodes.

Externally, there is speculation that TSMC’s 2nm process will employ nanosheet Gate-All-Around (GAA) transistor architecture for the first time, while Samsung has already adopted GAA technology at the 3nm node. Whether this can give Samsung a competitive edge over TSMC remains to be seen. However, due to the high technical complexity, introducing GAA technology in the early stages of development may face significant yield issues.

What is GAA, and how does it differ from the past FinFET technology?

Based on transistor structure, electrons enter from the source and move towards the drain, with their passage controlled by a metal gate (depicted in green). However, as chip miniaturization continues and the line width of the metal gate shrinks, typically below 20 nanometers, electrons may leak, causing electrical leakage and short circuits. This led to the invention of FinFET technology.

(Source: Applied Materials)

FinFET technology involves standing the source and drain regions vertically (depicted in gray), increasing the contact area with the metal gate. This provides strict control over electrons, preventing them from leaking. The vertical structure resembles a fish fin, hence the name “FinFET.”

However, as the technology scales below 3 nanometers, continuing to use FinFET processes may encounter physical limitations, leading to electrical leakage. To address this, fins need to be transitioned from vertical to horizontal, increasing the contact area even further. This results in the concept of “Gate-All-Around Field-Effect Transistor” (GAAFET).

Samsung began researching GAA architecture early and collaborated with IBM and GlobalFoundries to publish related papers in 2017. TSMC is also prepared to employ nanosheet transistor technology when moving to the 2nm node. However, due to the technical challenges of GAA, the development and production timeline may be delayed. Combined with reports of delays in 2nm fab construction, mass production is likely to be postponed until 2026.

TSMC N2 Nanosheet Concept Image. (Source: Screenshot from the video)

TSMC previously announced in November 2021 that it plans to establish two wafer fabrication plants for the 7nm and 28nm processes in Kaohsiung, a southern city of Taiwan. Construction was set to begin in 2022, with official production expected to commence in 2024. However, following the announcement, there have been changes in the progress of the Kaohsiung plant development.

Firstly, there were reports of adjustments to the 7nm plant by the end of 2022, in response to weakened demand in the smartphone and PC markets. Subsequently, there were also reports of changes to the 28nm plant’s plans.

It wasn’t until TSMC’s Q1 2023 earnings conference that they officially announced the adjustment of the Kaohsiung 28nm plant’s construction plans, focusing on capacity enhancement for more advanced process technologies.

At the time, TSMC didn’t specify the exact advanced process that would be introduced, only emphasizing that the construction of the wafer fab would proceed as planned. This triggered market speculation that TSMC was likely to adopt the advanced 2nm process technology at the Kaohsiung plant, in response to the rapidly growing demand in the artificial intelligence market.

This week, TSMC confirmed that the Kaohsiung plant will adopt the 2nm process technology. TSMC stated that the construction of the wafer fab in Kaohsiung will proceed as usual, but the previous expansion plans will be adjusted to accommodate the production of the 2nm advanced process technology, in response to strong market demand for advanced processes.

As for the specific details and contents of the plant development, they have not been further disclosed at this stage. According to TSMC’s plans, mass production of the 2nm process is expected to begin in 2025, with production bases including the previously announced Hsinchu and Taichung facilities, as well as the newly announced Kaohsiung facility.

(Photo credit: TSMC)

According to media reports, in response to the booming demand in the artificial intelligence market, TSMC has altered its Kaohsiung factory plan. Originally scheduled for a 28-nanometer mature process, the factory will now be equipped with a 2-nanometer advanced process, with mass production expected to commence in the latter half of 2025. The official announcement of this factory plan is imminent.

During a investor conference held on July 20th, TSMC refrained from making any comments, citing the current quiet period. As reported by “Central News Agency,” Kaohsiung Mayor Chen Chi-mai expressed the city government’s respect for TSMC and pledged full assistance. However, it is worth noting that the 2-nanometer process requires more funding compared to the 28-nanometer process, and TSMC has already informed the Kaohsiung city government, seeking support in terms of water and power supply.

Official data indicates that TSMC’s 2-nanometer process offers a 10% to 15% performance improvement at the same power consumption or a 20% to 30% reduction in power consumption at the same performance level compared to the 3-nanometer process. The primary production base for the 2-nanometer process will be located in Hsinchu’s Baoshan area, with plans to construct four fabs. The trial production is scheduled for 2024, followed by mass production in the latter half of 2025.

(Photo credit: TSMC)