Though still be struggling with low yield rates in 3nm, Samsung is reportedly ramping up its efforts to prepare for the mass production of 2nm and 1.4nm to compete with its longtime rival, TSMC. Citing industrial sources on Oct. 3^rd, Business Korea reveals that the South Korean foundry giant is introducing equipment at the Hwaseong plant to establish a 2nm production line, while it also plans to set up a 1.4nm line in its Pyeongtaek 2 plant next year.

According to the report, this initiative is in line with Samsung’s goal to mass produce 2nm in 2025 and 1.4nm by 2027.

In terms of the capacity expansion of 2nm, Samsung aims to install a capacity of 7,000 wafers per month by the first quarter of next year in its S3 foundry line at Hwaseong, Business Korea states. It is worth noting that the existing 3nm line at S3 is expected to be fully converted to a 2nm line by the end of next year.

Then, starting in the second quarter of next year, Samsung plans to set up a 1.4nm production line at the S5 facility in its Pyeongtaek 2 plant, with a capacity of approximately 2,000 to 3,000 wafers per month, according to the report.

Unlike the aggressive expansion for its advanced nodes in South Korea, Samsung’s foundry project in Taylor, Texas, seems to be in stagnant. The company had reportedly planned to begin mass production of below-4nm nodes there by the end of 2024, but this has somehow been pushed back to 2026, which reflects the possible yield issues regarding 3nm node with GAA architecture Samsung has been eager to solve, the report suggests.

Due to a decline in client orders, Samsung’s management has decided to convert the foundry line at its Pyeongtaek 4 plant into DRAM facilities, the report points out. Additionally, the Pyeongtaek 3 plant, which features a 4nm line, has decreased its scale of operation for the same reason.

Analysts cited by the report estimate that Samsung Foundry might incur a deficit of several hundred billion won in the third quarter of this year, underscoring the financial pressures the company is experiencing.

As the delay of the 3nm Exynos seems to be irreversible, securing the success of 2nm has become a top priority for Samsung. Business Korea indicates that the testing of Samsung’s 2nm will be conducted on the next-generation Exynos chip, codenamed “Tethys.” Evaluations may also be said to extend to chips from Qualcomm, Japan’s Preferred Networks (PFN), and Ambarella.

Read more

• [News] Samsung Reportedly Suspends Construction and Contract Plans for Pyeongtaek P4 and Taylor Plant 2
• [News] Samsung Reportedly Buckling Under Pressure, with Plans to Cut Overseas Workforce by Up to 30%

(Photo credit: Samsung)

As TSMC has reportedly begun trial production of 2nm chips in its Baoshan Plant in Hsinchu, northern Taiwan, the schedule of mass producing 2nm in 2025 remains on track. A report by Commercial Times reveals that the price of 2nm wafers is expected to double compared to 4/5nm, which may exceed USD 30,000 per wafer.

While the yield rates for advanced nodes of Intel and Samsung are rumored to be relatively low, the rising price of 2nm wafers reflects TSMC’s market monopoly as well as its strong pricing power, the report notes.

Citing comments by sources from semiconductor companies, the report states that fabs have invested heavily in advanced processes. For instance, the R&D investment of 3nm may exceed USD 4 billion, with key partners in TSMC’s supply chain, such as Taiwanese IP providers and material suppliers, playing a critical role.

On the other hand, executives from IC design houses cited by the report reveal that even from the perspective of IC design, the R&D cost for advanced nodes remains high. For instance, the development cost for 28nm is approximately USD 50 million, while 16nm may require an investment of USD 100 million. For 5nm, the R&D cost has soared to USD 550 million, if the expenditure on IP licensing, software verification, and design architecture are factored in.

According to the report, foundries have invested even more, with research institutions estimating that R&D expenses for 3nm may range from USD 4 billion to USD 5 billion. Additionally, constructing a 3nm fab is expected to cost at least USD 15 billion to USD 20 billion. All these factors may lead to the high pricing of wafers in the advanced nodes.

Therefore, for a foundry, the development of a new-generation of node involves massive efforts, and needed to be supported by partners in three key sectors: equipment, software (including IP and EDA tools), and materials, the report notes. Once their products have been validated by the foundry, suppliers can usually secure long-term partnership.

With 2nm set to debut in 2025, TSMC’s key suppliers are expected to see explosive profit growth, the report indicates. According to the report, Taiwanese IP firm M31, for example, has already developed IP that supports the 2nm platform for both smartphones and high-performance computing. Likewise, eMemory has disclosed that it is collaborating with leading foundries to develop 2nm.

On the other hand, as 2nm processes require thinner wafers, Taiwan-based materials companies, such as Kinik and Phoenix Silicon International Corp., have entered the markets of diamond discs and reclaimed wafers.

According to the report, in terms of reclaimed wafers, the market value for 2nm is approximately 4.6 times that of 28nm. In addition, the number of dummy wafers will also increase in advanced processes, which benefit suppliers with more volume and higher average prices.

Read more

• [News] TSMC Reportedly Mulls to Offer Discounts on Mature Nodes, Particular for 7nm/14nm Orders
• [News] TSMC’s Newly Acquired AP8 Facility in Southern Taiwan Rumored to Start Production in 2H25

(Photo credit: TSMC)

Japanese government-backed foundry Rapidus aims to begin mass production of 2nm chips by 2027. According to a MoneyDJ report, existing shareholders like Sony and NAND Flash giant Kioxia are reportedly considering additional investments to support the company’s funding needs.

The Japan Times cited sources confirming that Sony and other current investors will provide further financial backing for Rapidus, which is focused on domestic production of next-generation semiconductors. These investments will be coordinated with financial institutions and the central government to help the Tokyo-based firm secure the necessary capital to start production by 2027.

Rapidus is aiming to raise ¥100 billion from the private sector and asked shareholders to confirm additional contributions, with a response deadline set for Friday.

Investors in Rapidus include Sony Group, NEC, NTT, Kioxia, MUFG Bank, Toyota, SoftBank, and Denso, with combined investments totaling ¥7.3 billion. Sony, NEC, NTT, and MUFG Bank are expected to participate in the additional funding round.

In the financial sector, Sumitomo Mitsui Banking, Mizuho Bank, and the Development Bank of Japan are also considering becoming new shareholders, with combined investments from these three lenders and MUFG Bank expected to reach ¥25 billion. The additional funding from both financial and non-financial companies is likely to begin as early as 2025.

Samsung’s foundry business has been facing difficulties with its advanced chip processes, particularly with its 3-nanometer production. According to a report from The Korea Times, the yield for Samsung’s 3nm process remained in the single digits until Q1 this year, causing delays in supplying engineering samples for its Exynos 2500 chipsets.

The same report notes that local analysts estimate Samsung’s yield for its 3-nanometer process improved to about 20% in the second quarter. Despite this progress, the yield rate is still significantly below the 60% threshold generally needed for mass production, creating challenges for the company in securing foundry orders.

Reflecting this situation, Samsung appears to have shifted its strategy for its newest facility, the P4 fab in Pyeongtaek, Gyeonggi Province. Instead of initially installing equipment for NAND and then moving to foundry products, Samsung is now prioritizing advanced DRAM memory production, such as high-bandwidth memory (HBM) chips. Industry sources cited by The Korea Times suggest that this shift comes as a result of weak demand for its foundry services. There is growing speculation that Samsung might even dedicate the P4 fab entirely to memory chip production, driven by the steady demand for HBM and other advanced memory types used in AI servers.

These developments also cast uncertainty on Samsung’s investment in its Taylor, Texas plant. The company had originally planned to begin mass production of 4-nanometer chips there next year, but this has now been pushed back to 2026. Although the yield for the 4nm process is reportedly stable, Samsung continues to face challenges in securing orders from fabless companies.

This situation has led to speculation that Samsung may pivot to focusing on more advanced 2-nanometer chips instead of 4-nanometer ones to attract orders for next-generation products. However, reports indicate that the company is also struggling to achieve high yields for both its 2nm and 3nm processes.

Low yields have been a key factor behind Samsung’s ongoing struggles in its foundry business, according to industry insiders cited by The Korea Times. While the company has managed to stabilize yields for its 4nm process, more advanced nodes like the second-generation 3nm and 2nm processes remain problematic.

Adding to the challenges, a report from Business Korea on September 11th highlighted that continued yield issues with the 2nm process have prompted Samsung to withdraw personnel from its Taylor, Texas plant, marking another setback for its advanced wafer foundry ambitions.

Read more

• [News] Samsung’s 2nm Yield Rate at Most 20%, Withdraws Personnel from Texas Taylor Plant

(Photo credit: Samsung)

While Samsung Electronics is said to be delivering an oversea workforce cut up to 30%, a report from Korean media outlet Business Korea on September 11th has added that persistent issues with its 2nm yield rate have led Samsung to decide to withdraw personnel from its Taylor, Texas plant, signaling another setback for its advanced wafer foundry business.

Originally envisioned as a mass production hub for advanced processes below 4nm, the Taylor facility’s strategic location near major tech companies was intended to attract U.S. clients. However, despite rapid development, Samsung continues to face 2nm yield issues, resulting in performance and production capacity falling short of its main competitor, TSMC.

Reportedly, Samsung’s wafer foundry yield is below 50%, particularly in processes below 3nm, while TSMC’s advanced process yield is around 60-70%. This gap has widened the market share difference between the two companies.

As per a report from TrendForce, TSMC held a 62.3% share of the global wafer foundry market in the second quarter, while Samsung’s market share was only 11.5%.

Industry sources cited by Business Korea further added that Samsung’s Gate-All-Around (GAA) yield is around 10-20%, which is insufficient for handling orders and mass production. Such yields have forced Samsung to reconsider its strategy and withdraw personnel from the Taylor plant, leaving only a minimal number of staff.

Samsung Electronics had signed a preliminary agreement to receive up to KRW 9 trillion in subsidies from the U.S. Chips Act. However, a key condition for receiving the funding is that the plant must operate smoothly, and Samsung’s current difficulties put this agreement at risk.

Reportedly, Samsung Chairman Lee Jae-Yong personally visited major equipment suppliers like ASML and Zeiss, hoping to achieve breakthroughs in process and yield improvements. However, there have been no significant results so far, and it remains uncertain when personnel might be reassigned back to the Taylor plant.

Read more

• [News] Samsung Reportedly Buckling Under Pressure, with Plans to Cut Overseas Workforce by Up to 30%
• [News] Samsung Signals Will to Collaborate with Other Foundries on Basedie

(Photo credit: Samsung)