On September 9, Indian tech blog PiunikaWeb cited a report from Tech & Leaks Zone, stating that rumors have hinting at Google’s preparation to exit Samsung Electronics’ wafer foundry business, Samsung Foundry, and switch to TSMC in 2025. The next two generations of Google’s custom Tensor processors are reportedly expected to use TSMC’s 3nm and 2nm processes, respectively.

As per the same report, Google’s Tensor G4 processor is being manufactured by Samsung Foundry using its 4nm process. However, the G4 offers only a slight upgrade compared to the Tensor G3 in the Pixel 8 smartphone, as the G4 continues to use Samsung’s older FO-PLP packaging technology instead of the newer FO-WLP packaging, which is more capable in preventing overheating.

On the other hand, Google’s Tensor G5, which will be used in the Pixel 10, is reportedly set to be manufactured by TSMC using the latest 3nm process and TSMC’s advanced InFO-POP packaging technology. The Tensor G6, which will support the Pixel 11 series, will also be produced by TSMC using 2nm process.

Notably, Apple had introduced an AI technical document in June, disclosed that two AI models supporting “Apple Intelligence” were trained in the cloud using Google’s custom-designed Tensor Processing Unit (TPU).

Per Google’s official website, the cost of using its most advanced TPU can be less than USD 2 per hour if reserved three years in advance. Google first introduced the TPU in 2015 for internal use, and it became available to the public in 2017.

Additionally, per a report from wccftech, Google’s ARM-based TPU v5p “Axion,” designed specifically for data centers, is also rumored to be manufactured using TSMC’s enhanced 3nm process, N3E.

Read more

• [News] Google’s Tensor G5 Reportedly Manufactured with TSMC’s 3nm and InFO-POP Packaging
• [News] Breaking Apple’s Monopoly – TSMC’s InFO Packaging Reportedly Adds Google Chips

(Photo credit: Google)

TSMC is set to offer a new round of its CyberShuttle prototyping service in September. According to sources cited in a report from Commercial Times, it’s revealed that, as per usual practice, there are two opportunities each year, in March and September, for customers to submit their projects. It is indicated that the highlight this time is expected to be the 2nm process, providing leading companies with an opportunity to gain an edge.

TSMC’s 2nm technology is progressing smoothly, with the new Hsinchu Baoshan plant on track for mass production next year. Previously, there were rumors indicating that Apple is considering adopting 2nm chips in 2025, with the iPhone 17 series potentially being among the first devices to use them.

Reportedly, both TSMC’s N2P and A16 technologies are expected to enter mass production in the second half of 2026, offering improvements in power efficiency and chip density.

ASIC companies are eagerly participating in CyberShuttle this time, even though customer intentions for the first 2nm tape-out are still unconfirmed. However, this technology will likely maintain TSMC’s leadership in advanced processes, securing its future technological advantage.

CyberShuttle, also known as MPW (Multi-Project Wafer), refers to the process of placing chips from different customers onto the same test wafer. This approach not only allows for the shared cost of photomasks but also enables rapid chip prototyping and verification, enhancing customers’ cost efficiency and operational effectiveness.

Based on TSMC’s official information, the CyberShuttle prototyping service significantly reduces NRE costs by covering the widest technology range (from 0.5um to 7nm) and the most frequent launch schedule (up to 10 shuttles per month), all through the Foundry segment’s most convenient on-line registration system.)

TSMC’s CyberShuttle prototyping service also validate the sub-circuit functionality and process compatibility of IP, standard cell libraries and I/Os, reducing prototype costs by up to 90%. TSMC states that their current CyberShuttle service covers the broadest range of technologies and can offer up to 10 shuttles per month.

TSMC’s 2nm technology is expected to make its debut in September, offering opportunities for test chips.

Per the report from Commercial Times, IC design companies have pointed out that, unlike the familiar FinFET (Fin Field-Effect Transistor) structure, the industry is transitioning to the Gate-All-Around FET (GAAFET) structure, making it crucial for the market to quickly adapt.

This also allows IC design companies to provide related products to end customers, demonstrating their 2nm design capabilities.

ASIC companies have also revealed that, based on CyberShuttle data, the number of advanced process projects below 7nm is relatively small, with mature processes still dominating.

This suggests that future competition will likely focus on a few leading companies. Those who miss the first wave of 2nm technology may fall behind their competitors by up to six months, making securing a spot on the Shuttle even more critical.

Read more

• [News] TSMC Reportedly to Raise 3nm & 5nm Prices Soon, Looking to Maintain Long-Term Profit Margins 
• [News] Apple Not Adopting TSMC 2nm for iPhone 17? A19 Pro Chip Rumored to Use N3P Process

(Photo credit: TSMC)

According to sources cited in a report from Commercial Times, in response to the global increase in chip orders and rapid AI development, TSMC is actively seeking available land to keep its most advanced process technologies in Taiwan.

Currently, TSMC has already planned three 2nm fabs at the Nanzih Technology Industrial Park in Kaohsiung, southern Taiwan.

Regarding the need for additional land to accommodate facilities for more advanced nodes beyond 2nm, the report notes that the Kaohsiung City Government has been proactively preparing by evaluating land availability, as well as water and electricity supply, for TSMC’s next-generation advanced technology production, specifically targeting the A14 (14 angstrom) process.

Yet, regarding the matter, TSMC has remained discreet and declined to comment on market rumors regarding the progress of expansion.

Reportedly, the Nanzih Park site has the capacity to accommodate up to five fabs for TSMC, and there are rumors that its fourth and fifth fabs are likely to focus on A14 process, although TSMC has yet to confirm this.

TSMC’s first 2nm process fab in Nanzih is expected to begin mass production in 2025. Per sources cited by the report, the node will be used in high-performance computing (HPC), smartphones, electric vehicles, and autonomous driving applications.

Earlier, concerns were raised about the progress of TSMC’s CoWoS advanced packaging plant due to the discovery of cultural heritage sites at the Chiayi Science Park.

However, sources cited by Commercial Times have pointed out that while there have been some delays due to cultural heritage issues, TSMC’s adjustment plan has been approved. The company will adjust its working procedures in order to proceed with construction according to the original schedule, with no changes to the completion timeline.

Read more

• [News] Samsung Expected to Unveil its 1nm Plan in June, Advancing it to 2026
• [News] Decipher TSMC’s Calm Take on High-NA EUV Lithography Machines: Who May Have the Last Laugh in the Angstrom Era?

(Photo credit: TSMC)

AI industry has been driving semiconductor industry to advance forward. Benefited from the surge in AI-driven demand for advanced process chip, foundry industry is experiencing a gradual turnaround, while demands for consumer chip and automotive chip have not yet fully recovered, and competition remains fierce in the mature process chip sector, representing a stark contrast within the wafer foundry industry.

• Financial Results Indicate Strong AI Development but Weak Automotive Terminal Demands

Recently, several major foundries released their Q2 financial reports and shared outlook on future market conditions.

For the second quarter ending June 30, TSMC reported consolidated revenue of approximately USD 20.82 billion, up 32.8% YoY and 10.3% QoQ, which was attributed to strong demand for its 3nm and 5nm technologies.

As per the financial report, revenue from advanced technologies (7nm and below) accounted for 67% of TSMC’s total wafer revenue in 2Q24. In terms of application areas, HPC has replaced mobile business as the core driver of the company’s growth, contributing 52% of revenue.

Additionally, although TSMC’s automotive electronics revenue grew 5% QoQ, the company warned of a potential downturn in the automotive market this year.

UMC reported Q2 revenue of TWD 56.8 billion, up 4% QoQ. UMC expected customer inventories in the communications, consumer electronics, and computer sectors to return to seasonal levels as usual in the second half of this year, and to reach healthy levels by the end of the year.

However, demand in the automotive end market remains weak, which may extend the period of inventory adjustment, with healthy levels anticipated only by the first quarter of next year.

On August 6, GlobalFoundries released its latest financial report.

In the second quarter of this year, the company achieved revenue of USD 1.63 billion, a year-on-year decrease of 12% and a quarter-on-quarter increase of 5%. Net profit was USD 155 million, a year-on-year decrease of 35% and a quarter-on-quarter increase of 16%.

Industry sources cited by the report from WeChat account DRAMeXchange believe that during the pandemic, customers in sectors such as IoT, mobile device, and data center accumulated high inventory, which impacted GlobalFoundries’ revenue.

Moreover, the company is experiencing a cyclical downturn due to soft demands in the automotive, industrial, and other sectors.

• Advanced Processes Continue to Thrive while Mature Processes Face Intense Competition

The adoption of AI generative models keeps on the rise, driving high demand for AI chip. In this context, advanced processes have been well-received, leading to price increase and production expansion.

TrendForce’s survey in June showed that TSMC is seeing full capacity utilization in its 5/4nm and 3nm nodes due to strong demand from AI applications, new PC platforms, HPC applications, and high-end smartphones.

Its capacity utilization is expected to exceed 100% in the second half of the year, with visibility extending into 2025. Given cost pressures from overseas expansion and rising electricity prices, TSMC plans to raise prices for its advanced processes, which are experiencing strong demand.

TSMC is seeing full capacity utilization in its 5/4nm and 3nm nodes due to strong demand from AI applications, new PC platforms, HPC applications, and high-end smartphones. Its capacity utilization is expected to exceed 100% in the second half of the year, with visibility extending into 2025.

Given cost pressures from overseas expansion and rising electricity prices, TSMC plans to raise prices for its advanced processes, which are experiencing strong demand.

As per other sources cited by the same report, TSMC informed customers of a price increase for 5/3nm process products in 2024 at the beginning of this year.

In late July, TSMC notified several customers that due to rising costs, prices for 5/3nm process products will increase again starting January 2025, and the increase will range from 3-8%, depending on the tape-out plan, product, and partnership.

Meanwhile, the surge in demand for advanced packaging driven by AI will also lead to higher CoWoS prices.

To seize the significant opportunities brought by AI, many companies are actively investing in advanced processes. Currently, the 3nm process is the most advanced in the industry.

Meanwhile, TSMC, Samsung, Intel, and Rapidus are vigorously promoting the construction of 2nm fabs. Previously, TSMC and Samsung intended to produce 2nm chip at scale in 2025, while Rapidus planed to start trial production in 2025.

Following 2nm, 1nm chip will be the next goal for these fabs. According to their plans, the industry is likely to see the mass production of 1nm chip from 2027 to 2030.

Unlike the rising prices and volume in advanced process chip, mature process chip faces some uncertainty due to weaker-than-expected recovery in end-user demand, and sees more intense competition among manufacturers.

TrendForce’s survey reveals that the capacity utilization rates of PSMC and Vanguard is expected to improve more than anticipated in the second half of the year. However, overall demand for mature processes remains weak, with average capacity utilization still around 70–80%—indicating no significant shortages.

TrendForce further pointed out that in 2024, concerns over global inflation and weak recovery in end-demand may result in inconsistent momentum in replenishing inventory. Many foundries might offer price incentives to attract customers and boost capacity utilization, leading to a decline in overall ASP.

Furthermore, a significant amount of new capacity is expected to come online in 2025, including TSMC JASM, PSMC P5, SMIC’s new Beijing/Shanghai plants, HHGrace Fab9, HLMC Fab10, and Nexchip N1A3.

This increase in mature process capacity could intensify competition and impact future pricing negotiations.

Read more

• [News] Intel and NVIDIA’s New Platform Orders Rolling Out, TSMC Unaffected by Market Turbulence
• Foundry Market Shows Mixed Conditions with Price Adjustments for Specific Chinese Processes and Anticipated Price Increases for Taiwanese Advanced Processes, Says TrendForce

(Photo credit: TSMC)

While surrounded by concerns raised by the USD 1.6 billion net loss in Q2 and the large-scale layoff plan, Intel has finally shared some good news. It announced on August 6^th that its next-gen 18A process has achieved a major milestone, and will start production in 2025.

The semiconductor giant states that the milestone has been achieved less than two quarters after tape-out, and confirms that two of its next-gen products, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), will be fabricated with the node. The first external customer is expected to tape out on Intel 18A in the first half of next year, according to its press release.

The company also gives an advance notice on the progress of the aforementioned two processors. According to Intel, Clearwater Forest will mark the industry’s first mass-produced, high-performance solution combining RibbonFET, PowerVia, and Foveros Direct 3D for higher density and power handling. In addition, Panther Lake DDR memory performance is already running at target frequency.

Earlier in July, Intel released the 18A Process Design Kit (PDK) 1.0, design tools that enable foundry customers to harness the capabilities of RibbonFET gate-all-around transistor architecture and PowerVia backside power delivery in their designs on Intel 18A.

It is worth noting that Intel’s 18A is the company’s second fabrication technology, following 20A, to employ RibbonFET and PowerVia. A report by Tom’s Hardware notes that compared to Intel’s 2nm-class node, 18A offers an optimized RibbonFET design and additional enhancements, resulting in a 10% increase in performance per watt, which makes it especially fitted for data center-class products that require significant power.

The report also notes that Intel 18A is a process that Intel Foundry’s potential customers are very interested in, as some believed it to be more competitive than TSMC’s 3nm and 2nm-class offerings, which are expected to be available between 2024 and 2025.

On the other hand, TSMC, the global foundry leader, said earlier in the earnings call that it’s 2nm (N2) node is progressing well, and will begin mass production in 2025. The company is also on track to launch the N2P and A16 processes in the second half of 2026.

Read more

• [News] NVIDIA’s Backup Plan? Intel Reportedly Secures Packaging Orders from the AI Giant
• [News] Intel’s Earnings Fall Short, Cutting Over 15% of Workforce

(Photo credit: Intel)