According to a report from Bloomberg, Jun Young-hyun, head of Samsung’s chip business, recently sent a stern warning to employees about the need to reform the company’s culture to avoid falling into a vicious cycle.

Jun stated that the recent improvement in Samsung’s performance was due to a rebound in the memory market. To sustain this progress, Samsung must take measures to eliminate communication barriers between departments and stop concealing or avoiding problems.

Earlier this week, Samsung announced its Q2 earnings, showcasing the fastest net profit growth since 2010. However, Jun Young-hyun highlighted several issues which may undermine Samsung’s long-term competitiveness.

He emphasized the need to rebuild the semiconductor division’s culture of vigorous debate, warning that relying solely on market recovery without restoring fundamental competitiveness would lead to a vicious cycle and repeating past mistakes.

Samsung is still striving to close the gap with its competitors. The company is working to improve the maturity of its 2nm process to meet the high-performance, low-power demands of advanced processes. Samsung’s the first-generation 3nm GAA process has achieved yield maturity and is set for mass production in the second half of the year.

In memory, Samsung is beginning to narrow the gap with SK Hynix in high-bandwidth memory (HBM). According to Bloomberg, Samsung has received certification for HBM3 chips from NVIDIA and expects to gain certification for the next-generation HBM3e within two to four months.

Jun emphasized that although Samsung is in a challenging situation, he is confident that with accumulated experience and technology, the company can quickly regain its competitive edge.

Read more

• [News] Samsung Sees Solid Demand for 3nm in 2H24, Aiming a Ninefold Increase in AI/HPC Sales by 2028
• [News] Samsung’s Q2 Profits Soar to USD 7.5 Billion, Seeing Strong Demand for HBM, DDR5 and Server SSD in 2H24

(Photo credit: Samsung)

According to a report from Commercial Times, IC design giant MediaTek is making its move into the AI accelerator sector. MediaTek CEO Rick Tsai emphasized that MediaTek aims to be the best partner for edge AI, focusing on advanced technologies and 3nm process to optimize the power consumption and efficiency of its SoCs (system-on-chips).

Tsai mentioned that MediaTek will unveil its Dimensity 9400 flagship series of chips in October, designed to perfectly support most large language models on the market. He expressed confidence in achieving a more than 50% year-over-year revenue increase for flagship devices.

For the ASIC (Application-Specific Integrated Circuit) market, MediaTek has confirmed its entry into the AI accelerator field and will integrate CPUs as needed. ASICs are expected to start the revenue contribution  in the second half of next year.

Additionally, the TAM (Total Addressable Market) for generative AI is still in its early stages. MediaTek focuses on providing leading interconnect capabilities, such as SerDes IP and Ethernet PHY.

Regarding AI technology in the smartphone sector, Rick Tsai believes that flagship smartphones are seeing an increase in ASP, and there is a gradual shift towards high-end smartphones in the Chinese market. He noted that Chinese brands are actively developing AI, particularly in model development, such as open-source models like LLaMA 3.

At MediaTek’s earnings call on July 31st, Rick Tsai noted that the company anticipates a return to normal seasonal patterns in the second half of the year. The outlook for the fourth quarter will largely depend on consumer product demand.

Regarding the outlook in the third quarter, MediaTek expects the revenue to be flattish, ranging from NTD 123.5 billion to NTD 132.4 billion, compared with NTD 127.27 billion last quarter. Gross margin is projected to slide to 45.5-48.5%, from 48.8%, down 3.6 percentage points quarter over quarter and up 1.3 percentage points year-over-year.

Aside from the boost expected from the Dimensity 9400 flagship release, the company’s fourth-quarter market demand is projected to be relatively moderate, which is why the annual outlook remains unchanged. MediaTek expects its full-year gross margin to be between 46% and 48%.

Regarding TSMC’s pricing adjustments, Rick Tsai remains unperturbed, noting that all industry peers face similar cost pressures. MediaTek aims to reflect cost increases through pricing, with a gross margin target of 47% for new products. Progress has also been made in 3nm and 2nm processes, and MediaTek has secured its capacity needs for 2025 with TSMC.

Moreover, MediaTek and NVIDIA are collaborating on automotive chips, with plans to launch their first chip in early 2025. Rick Tsai mentioned that details are yet to be disclosed, but significant advancements in the automotive sector are expected between 2027 and 2028.

Read more

• [News] MediaTek Reportedly Designing ARM-Based Chips for Microsoft’s AI PCs, Launch Expected by End of Next Year
• [News] MediaTek Reportedly Partners with Meta, Entering the Battleground of AI against Apple and Qualcomm

(Photo credit: MediaTek)

As the industry is entering the Angstrom era with semiconductor giants eagerly applying EUV machines to the advanced nodes, more details about Samsung’s 2nm have surfaced. According to the latest report by TheElec, Samsung’s 2nm process will feature 30% more extreme ultraviolet (EUV) layers than the 3nm node.

The report notes that Samsung’s 3nm node has 20 EUV mask layers, while the layers of the 2nm node will be increased to late-20. As the cost of manufacturing rises with the number of EUV mask layers, whether the wafer average selling price of Samsung’s 2nm will significantly increase attracts attention.

According to the report, the South Korean semiconductor giant first implemented EUV technology in its logic process nodes with 7nm in 2018. Since then, Samsung has increased the number of EUV layers or process steps with each subsequent node, moving from 5nm to 3nm. The report also states that Samsung’s 1.4nm process, set to begin production in 2027, is expected to feature over 30 EUV layers.

Meanwhile, Samsung is also using EUV in its DRAM production. For its Gen 6 10nm DRAM, Samsung has implemented up to 7 EUV layers, compared to 5 layers used by SK Hynix, TheElec states.

In comparison, according to an earlier report by AnandTech, TSMC’s standard N3 node includes up to 25 EUV layers. TSMC employs EUV double-patterning on some of these layers to achieve greater logic and SRAM transistor density compared to its N5 node.

It is also worth noting that as EUV layers increase with each node, foundries are vying to secure more EUV machines from ASML. The Dutch lithography equipment giant is said to ship over 70 EUV machines to TSMC in 2024 and 2025 in response to the strong demand of 2nm and 3nm, according to a report by MoneyDJ.

Read more

• [News] Samsung Officially Secures Its First 2nm Order, Making AI Chips for Preferred Networks
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)

After Samsung announced a major breakthrough in 2nm, securing the first batch of orders from Japanese AI company Preferred Networks, its rival TSMC is also advancing. According to reports from Wccftech and ET News, TSMC is set to begin trial production of 2nm chips next week, which would reportedly be used in the upcoming iPhone 17 lineup in 2025.

The reports note that the trial production will be conducted in TSMC’s Baoshan Plant in Hsinchu, northern Taiwan, as facilities have been brought in during the second quarter. The iPhone 17 lineup is rumored to be the first to feature TSMC’s 2nm chips. Following that, the chips will likely be used in the 14-inch and 16-inch MacBook Pro models.

According to a previous report by MoneyDJ, TSMC’s 2nm production bases are located in Hsinchu Science Park and Kaohsiung, southern Taiwan, while the mass production is expected to kick off in Hsinchu first, with an initial monthly capacity of approximately 30,000 to 35,000 wafers.

Apple and TSMC share a long history of partnership, as the smartphone giant’s A17 Pro, M3 and M4 chips are all manufactured with TSMC’s 3nm node. As TSMC reportedly plans to enter 2nm trial production next week for Apple’s M5 chip, the company’s target for 2nm to enter mass production in 2025 would be on schedule, Wccftech notes.

According to Wccftech, The M5 chip, compared to its predecessor M4, is expected to have performance increase of 10 to 15 percent and a power consumption reduction of up to 30 percent compared to current 3nm-based chips.

Regarding the progress of other semiconductor heavyweights on 2nm, Samsung is said to commence mass production of 2nm chips for mobile devices by 2025. The initial SF2 2nm process will be ready next year, followed by an enhanced version, SF2P, in 2026. Its latest 2nm process, SF2Z, has incorporated optimized backside power delivery network (BSPDN) technology, and will enter mass production in 2027.

On the other hand, Intel’s 20A manufacturing technology (2nm) is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and BSPDN.

Read more

• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] TSMC Reportedly Invests over USD 12.3 Billion in EUV, Advancing in 2nm Production

(Photo credit: Apple)

Samsung Electronics has received the first client for its 2nm process. According to the official press release from Samsung on July 9th, Samsung Electronics will provide turnkey semiconductor solutions using the 2nm process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Japanese AI company Preferred Networks.

Per a previous report by SamMobile, Samsung is set to commence mass production of 2nm chips for mobile devices by 2025. The initial SF2 2nm process will be ready next year, followed by an enhanced version, SF2P, in 2026. In addition, according to Samsung’s press release, its latest 2nm process, SF2Z, has incorporated optimized backside power delivery network (BSPDN) technology, and will enter mass production in 2027.

Preferred Networks was founded in 2014 and is in the field of AI deep learning development. The company has attracted significant investments from major Japanese industrial enterprises such as Toyota, NTT, and Fanuc. The order placed with Samsung’s foundry division for 2-nanometer AI chips also includes HBM and advanced packaging.

As per the official release, Junichiro Makino, VP and Chief Technology Officer (CTO) of Computing Architecture at Preferred Networks stated that as Samsung Electronics’ 2nm GAA process will significantly support Preferred Networks’ ongoing efforts to build highly energy-efficient, high-performance computing hardware that meets the ever-growing computing demands from generative AI technologies, especially large language models.

Driven by the strong demand from AI chips, Samsung expects the revenue of global chip industry to grow to USD 778 billion by 2028, according to Siyoung Choi, President and General Manager of the Foundry Business in Samsung, the report noted.

Read more

• [News] Samsung Unveils Next-gen 2nm Node Roadmap; SF2Z with Backside Power Delivery to Enter Production in 2027
• [News] Samsung Secures 2-Nanometer Order from Japanese AI Startup Preferred Networks

(Photo credit: Samsung)