Apple currently uses TSMC’s 3-nanometer process for multiple chipsets. According to a report from wccftech, the iPhone 17 chipset will not adopt the 2-nanometer process. Instead, the A19 Pro chip, expected in 2025, is reportedly maintaining the 3-nanometer technology.

The same report suggests that the Apple A19 Pro chip is considering TSMC’s N3P process and may be featured in the iPhone 17 Pro and iPhone 17 Pro Max. TSMC aims to ramp up its 3-nanometer wafer capacity to 100,000 units by the end of 2024.

TSMC began trial production of 2-nanometer chips as early as June 2023. However, Apple’s A18 Pro chip for the iPhone 16 Pro and iPhone 16 Pro Max might use the N3E process. As for next year’s iPhone 17, its A19 Pro chip is likely to adopt TSMC’s N3P technology.

As per MoneyDJ’s report, it is currently expected that Apple’s iPhone 18 series, slated for release in 2026, will feature the first-ever 2-nanometer chip. Besides Apple, other 2-nanometer customers include Intel, with interest also anticipated from AMD, NVIDIA, and MediaTek. Looking at the process roadmap, this year’s iPhone 16 will use N3E, while next year’s model will adopt N3P. Thus, the first consumer product leveraging TSMC’s 2nm process is anticipated to launch in 2026.

Meanwhile, Apple is said to be striving to stay ahead of competitors and exploring alternative packaging technologies like 3DFabric with its foundry partner. A rumor from the account Yeux1122 has suggested that Apple is already delving into SoIC (Small Outline Integrated Circuit) packaging.

TSMC, the leading semiconductor foundry, recently announced plans to establish a 2nm production line in the US, while attention remains on expansion progress in Taiwan.

According to a report from MoneyDJ, it has indicated that the 2nm fab in Hsinchu’s Baoshan is proceeding steadily as planned, and the 2nm fab in Kaohsiung is gaining momentum, with the first tool-in expected by year-end.

Initially, both fabs will achieve a monthly capacity of approximately 30,000 to 35,000 wafers. By 2027, their combined capacity is set to exceed 100,000 wafers, marking the mainstream transition to the next generation of processes.

As per industry sources cited by MoneyDJ, TSMC’s 2nm production bases are located in Hsinchu Science Park and Kaohsiung, and Baoshan’s Phase 2 will begin tool-in in the second quarter, with a “mini line” to be established by year-end and mass production targeted for Q4 2025, starting with an initial monthly capacity of approximately 30,000 to 35,000 wafers.

Meanwhile, the Kaohsiung plant is expected to commence equipment installation by year-end, ahead of the original schedule, aiming for mass production in the first half of 2026 with an initial monthly capacity plan similar to Baoshan’s 30,000 to 35,000 wafers.

The same sources also indicate that after the formal mass production of the Baoshan and Kaohsiung plants, they will enter the capacity ramp-up phase, aiming to achieve a combined capacity of around 110,000 to 120,000 wafers per month by 2027. Both fabs will produce the first-generation 2nm and the second-generation N2P with backside power rail technology. The next-generation 1.4nm (A14) is expected to commence production in the second half of 2027, potentially located in Taichung.

In the 2nm client landscape, Apple remains a frontrunner, earmarking the technology for flagship smartphones. Intel has also expressed interest, with AMD, NVIDIA, and MediaTek expected to follow suit.

Looking at the process roadmap, this year’s iPhone 16 will use N3E, while next year’s model will adopt N3P. Thus, the first consumer product leveraging TSMC’s 2nm process is anticipated to launch in 2026.

Previously at its earnings call, TSMC disclosed the development of a backside power rail solution for N2, tailored for HPC applications.

TSMC is scheduled to hold an earnings call on April 18th. It is anticipated that the related topics around its 2nm process will also be the focus of attention on the day of the conference.

Read more

• [News] TSMC Receives USD 6.6 Billion for Chipmaking from the US Government, Commits to Constructing Third Fab
• [News] TSMC’s Latest Statement Indicates Equipment Largely Recovered, Revenue Forecast Unchange

(Photo credit: TSMC)

The U.S. government officially announced today that it will provide a USD 6.6 billion subsidy to TSMC, and in its latest press release, confirmed that TSMC will build its third fab in Arizona, USA, with total investment rising to USD 65 billion.

Due to various construction and chip incentive factors, TSMC announced in 2023 that the commissioning of Fab 21 (Fab 1) in Arizona, originally planned for 2024, was postponed to 2025. In January 2024, it was further announced that Fab 2 (originally scheduled to commence operations in 2026) would not begin mass production until 2027 or 2028.

According to the latest information released by TSMC, Arizona’s first fab is on track to begin production leveraging 4nm technology in first half of 2025. The second fab will produce the world’s most advanced 2nm process technology with next-generation nanosheet transistors in addition to the previously announced 3nm technology, with production beginning in 2028.

The third fab will produce chips using 2nm or more advanced processes, with production beginning by the end of the decade. Each of the three fabs, like all of TSMC’s advanced fabs, will have cleanroom area approximately double the size of an industry standard logic fab.

TSMC’s confirmation of plans to build a third fab in Arizona signifies its move towards more advanced semiconductor production in the United States. However, based on the current construction progress in the U.S., market estimates suggest that mass production may not begin until after 2030.

“The CHIPS and Science Act provides TSMC the opportunity to make this unprecedented investment and to offer our foundry service of the most advanced manufacturing technologies in the United States,” said TSMC Chairman Dr. Mark Liu.

“Our U.S. operations allow us to better support our U.S. customers, which include several of the world’s leading technology companies. Our U.S. operations will also expand our capability to trailblaze future advancements in semiconductor technology.”

“We are honored to support our customers who have been pioneers in mobile, artificial intelligence and high-performance computing, whether in chip design, hardware systems or software, algorithms, and large language models,” said TSMC CEO Dr. C.C. Wei.

“They are the innovators driving demand for the most advanced silicon that TSMC can provide. As their foundry partner, we will help them unleash their innovations by increasing capacity for leading-edge technology through TSMC Arizona. We are thrilled by the progress of our Arizona site to date and are committed to its long-term success.”

This market news emerged shortly after the major earthquake in Hualien, Taiwan, leading to speculation within the industry about its connection to the earthquake. Nevertheless, according to industry sources, the recent news about the Fab 3 project in Arizona was not triggered by the recent earthquake but was actually finalized by TSMC after discussions with the U.S. government on future plans.

Read more

• [News] TSMC’s Latest Statement Indicates Equipment Largely Recovered, Revenue Forecast Unchanged
• [News] TSMC’s US Fab Reportedly Eyeing for Early Mass Production

(Photo credit: TSMC)

As the demand for AI is becoming urgent, according to industry sources cited by the ChinaTimes News, TSMC’s Fab20 P1 plant in Hsinchu’s Baoshan area will undergo equipment installation engineering in April to warm up for mass production of the GAA (gate-all-around) architecture.

Reportedly, it is expected that Baoshan P1, P2, and the three fabs scheduled for advanced process production in Kaohsiung will all commence mass production in 2025, attracting customers such as Apple, NVIDIA, AMD, and Qualcomm to compete for production capacity.

Regarding this rumor, TSMC declined to comment.

Per the industry sources cited by the same report, whether wafer manufacturing is profitable is depending on the yield after mass production. The key lies in the speed at which the yield improves; the longer it takes and the higher the cost, the more challenging it becomes.

As per the same report, TSMC is said to be accelerating its entry into the 2-nanometer realm in April, aiming to shorten the time required for yield improvement in advanced processes. This move not only poses a continuous threat to Samsung and Intel but also widens TSMC’s leading edge.

Industry sources cited by the ChinaTimes’ report have revealed that TSMC has prepared for first tool-in at P1, with trial production expected in the fourth quarter this year and mass production in the second quarter of next year. Equipment manufacturers indicate that they have already deployed personnel and conducted preparatory training in response to TSMC’s customized demands.

As a new milestone in chip manufacturing processes, the 2-nanometer node will provide higher performance and lower power consumption. It adopts Nanosheet technology structure and further develops backside power rail technology. TSMC believes that the 2-nanometer node will enable it to maintain its technological leadership and seize the growth opportunities in AI.

In fact, the cost of producing 2-nanometer chips is exceptionally high. Per the report citing sources, compared to the 3-nanometer node, costs are expected to increase by 50%, with the per-wafer cost reaching USD 30,000. Therefore, the initial adopters are expected to be smartphone chip clients, notably Apple.

Previously, per a report from the media outlet wccftech, Apple’s iPhone, Mac, iPad, and other devices will be the first users of TSMC’s 2nm process. Apple will leverage TSMC’s 2nm process technology to enhance chip performance and reduce power consumption. This advancement is expected to result in longer battery life for future Apple products, such as the iPhone and MacBook.

Unlike with the 3-nanometer node, the complexity of the design means customers must start collaborating with TSMC earlier in the development process. Market speculations suggest that many clients such as MediaTek, Qualcomm, AMD, and NVIDIA have already begun cooperation. TSMC’s earnings call also emphasized that the number of customers for N2 is higher than that for N3 at the same stage of development.

The Fab 20 facility is expected to begin receiving related equipment for 2nm production as early as April, with plans to transition to GAA (Gate-All-Around) technology from FinFET for 2nm mass production by 2025.

The competition in the development of 2-nanometer technology is fierce. ASML plans to produce 10 2-nanometer EUV lithography machines this year, with Intel already reserving 6 of them. Additionally, Japan has mobilized its national efforts to establish Rapidus Semiconductor Manufacturing, which also aims to compete in the 2-nanometer process.

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• [News] Intensified Competition in the Semiconductor Industry for 2nm Technology Dominance, Potentially Reshaping the Global Foundry Market
• [News] TSMC’s Primary Client for 2nm Chips Expected to be Apple, Set to Debut with iPhone 17 Lineup Next Year

Shortly after the release of the MacBook Air with the built-in M3 chip, a report from MacRumors has cited the report that Apple is already working on the development of the next-generation M4 chip, expected to be launched next year.

As per Mark Gurman revealed in a Q&A with Bloomberg, Apple has officially commenced the development of the M4 chip, which is expected to debut alongside the next-generation MacBook Pro. Reportedly, there’s a possibility that the M4 chip may adopt TSMC’s 2nm process. TSMC’s related process is scheduled to undergo first tool-in this year and commence mass production next year.

As per MacRumors’ report, following the introduction of the first in-house developed M1 chip by Apple in November 2020, Apple has consistently pursued chip upgrades. In June 2022, Apple unveiled the M2 chip, followed by the release of the M3 chip at the end of October last year.

With approximately a year and a half gap between each generation of chips, it is speculated by MacRumors that Apple will unveil the M4 chip in the first half of next year. Some sources cited in the report also believe that Apple’s accumulated experience in chip development in recent years may enable them to shorten the development timeline, potentially leading to the announcement of the M4 chip by the end of this year.

However, compared to the 3nm process used in the M3 chip, the 3nm process of the M4 chip could be an upgraded version, with improvements in both computational capability and energy efficiency.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures and is anticipated to commence mass production in 2025, so the M4 chip may still adopt the 3nm process.

As for TSMC’s 2-nanometer process, a previous report from wccftech has indicated that Apple is expected to adopt the 2nm process for chip production in the iPhone 17 by 2025.

Read more

• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] Apple Reportedly Places Large Orders for TSMC’s 3nm While Simultaneously Securing Significant Advanced Packaging Capacity

(Photo credit: Apple)