TSMC announced during its briefing on the 18th that, due to robust demand in the 2-nanometer market, it plans to add another fab to the initially planned two fabs in Kaohsiung.

The company intends to use the 2-nanometer process for all three fabs in Kaohsiung, in addition to the originally planned 2-nanometer fab in Hsinchu’s Baoshan. Furthermore, the land recently acquired in Hsinchu Science Park will also be designated for a 2-nanometer fab. This reflects the strong preference for the 2-nanometer process among customers and underscores TSMC’s confidence in its in-house 2-nanometer process technology.

According to a report by TechNews following the briefing on the 18th, TSMC’s CFO Wendell Huang, stated in a media gathering that the strong demand in the high-performance computing and smartphone markets prompted the decision to increase the number of fabs in Kaohsiung from the originally planned two to three. Once the three 2-nanometer fabs are in full production, Kaohsiung will become a crucial manufacturing hub for TSMC’s 2-nanometer process.

In addition, with the recent approval from the Ministry of the Interior’s Urban Planning Commission, the land in Hsinchu Science Park designated for TSMC’s use, expected to be available in June 2024, is also being planned for a 2-nanometer fab.

Recent market reports suggest that TSMC, the leading semiconductor foundry, is set to proceed as scheduled with its plan to adopt the GAA (Gate-All-Around) architecture from the 2-nanometer process onward.

The P1 wafer fab in Baoshan, located in the Hsinchu Science Park, is anticipated to begin equipment installation as early as April 2024, while the Kaohsiung fab is projected to commence production using the GAA architecture for the 2-nanometer process technology in 2025.

Furthermore, in response to Intel securing the first High-NA EUV exposure equipment from ASML for its 18A advanced process, TSMC has indicated that it is also planning for High-NA EUV exposure equipment. However, the current timeline anticipates engineering verification of the High-NA EUV exposure equipment in 2024, with gradual integration into the manufacturing process set to follow.

(Image: TSMC)

The global foundry advanced process battle is reigniting, as reported by the Commercial Times. TSMC’s 2-nanometer process at the Baoshan P1 wafer fab in Hsinchu is set to commence equipment installation as early as April, incorporating a new Gate-All-Around (GAA) transistor architecture and aiming for mass production in 2025.

Additionally, expansion plans for Baoshan P2 and the Kaohsiung fab are projected to join in 2025, with evaluations underway for Phase 2 in the Central Taiwan Science Park. The competition with Samsung and Intel in the most advanced process is intensifying.

Semiconductor industry sources note the ongoing progress in global foundry advanced processes, with Samsung entering GAA architecture early at 3 nanometers, though facing yield challenges, while Intel anticipates mass production of its RibbonFET architecture at 20A this year.

In response to fierce competition, TSMC must accelerate its pace. The ‘Gate-All-Around’ (GAA) technology is a critical factor determining whether chip processing power will double within 1.5 to 2 years.

As per the report, Samsung’s attempt to lead in the 3-nanometer chip segment, transitioning from traditional FinFET, has faced stability issues in yield, hampering customer adoption, and giving TSMC confidence in its 3-nanometer progress. This also highlights the increased complexity in transitioning from 2D to 3D chip designs with GAA transistor architecture.

Furthermore, Intel is intensifying its efforts to catch up, planning to launch Intel 20A in the first half of the year and Intel 18A in the second half. However, it is speculated that Intel 20A will be exclusively used for Intel’s own products, maintaining a close collaboration with TSMC.

TSMC, adopting a cautious approach, benefits from a more advantageous cost structure by minimizing changes in production tools within the same process technology and manufacturing flow. For customers, altering designs during advanced process development incurs significant time and economic costs.

Supply chain sources reveal that TSMC finalized various parameters for its 2-nanometer process at the end of last year, confirming specialty gases and equipment. Contracts are gradually being signed, with equipment installation at the Baoshan P1 fab scheduled to commence in April. Equipment industry sources suggest that TSMC’s process advancement is progressing rapidly as expected, speculating that there will be updates on the Baoshan P2 fab later this year.

(Image: TSMC)

With the successful mass production of TSMC’s 3nm process and preparations for the upcoming 2nm process, recent reports suggest that TSMC has awarded a special contribution bonus to its research and development team in December, acknowledging the hard work of its employees.

In response to the news about the special contribution bonuses in December, TSMC stated that the company has always upheld the belief that “employees are the company’s most important assets” and this move is part of the ongoing commitment to taking care of its workforce.

According to reports citing from the industry sources, TSMC successfully commenced production of 3nm chips last year, and mass production is on track for the latter half of this year. Following this, advancements are being made in advanced processes, including 2nm and the development of processes such as A14 (1.4nm) and A10.

Specifically, after smooth research and development trials of the 2nm process this year, it will be integrated into the completed construction of Fab 20 in Baoshan, Hsinchu. The team at this facility is gearing up for risk production in 2024 and aims for mass production in 2025. A14 is expected to undergo trial production and mass production between 2027 and 2028.

TSMC has previously mentioned in its Earning Conference that the 2nm process technology will adopt a Nanosheet transistor structure, enhancing performance to meet the growing demand for energy-efficient computing.

Additionally, the 2nm family has developed backside power rail solution, particularly suitable for high-speed computing applications. The goal is to launch this solution for customer adoption in the latter half of 2025 and begin mass production in 2026.

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(Photo credit: TSMC)

As TSMC, Samsung, and Intel compete fiercely in the race for 2nm advanced processes, a new wave of the “battle for crucial equipment” is simultaneously unfolding.

According to South Korean reports, ASML, the leader in semiconductor advanced lithography equipment, plans to manufacture ten equipment capable of producing 2nm chips next year, while aiming to increase its annual production capacity to 20 devices in the coming years.

Intel has secured up to six of the 10, taking the lead, while Samsung is also actively pursuing the procurement of the equipment. TSMC faces significant pressure in this competitive landscape.

South Korean tech media SamMobile has unveiled that as major semiconductor manufacturers announce plans to start producing 2nm chips in 2025, ASML is set to unveil equipment capable of manufacturing chips using the 2nm process in the coming months.

The latest extreme ultraviolet (EUV) lithography equipment is expected to increase the numerical aperture (NA) from 0.33 to 0.55. This enhancement improves the light-collecting capability of the optical system, enabling semiconductor fabs to utilize advanced patterning techniques for the production of 2nm process chips.

ASML is the sole global manufacturer of advanced EUV equipment for processes at 7nm. These equipment are not only expensive, costing several million dollars each, but they also have limited production capacity.

It has led to high demand from major semiconductor manufacturers like Samsung, Intel, and TSMC. Currently, only five chipmakers globally, including TSMC, Samsung, SK Hynix, Intel, and Micron, require EUV equipment, with TSMC accounting for 70% of EUV purchases.

Consequently, Samsung is actively pursuing collaboration and has signed a historic agreement with ASML to jointly invest KRW 1 trillion (approximately USD 755 million) in establishing a research and development facility in South Korea.

This collaboration aims to contribute to the development of Samsung’s 2nm process. Samsung plans to commence the production of 2nm process chips by the end of 2025 after acquiring the 2nm manufacturing equipment.

Samsung Electronics Vice Chairman Kyung Kye-hyun, who heads the Device Solutions Division, emphasized that the new agreement with ASML will assist Samsung in acquiring the next-generation high NA EUV equipment.

Kyung said, “Samsung has secured a priority over the High-NA equipment technology. (From the trip), I believe we created an opportunity for us to optimize the usage of High-NA technology for our production of DRAM memory chips and logic chips in the long term.”

On the Intel front, as part of its IDM 2.0 strategy, it is executing a 5 nodes in four years process development plan. Intel emphasizes that its Intel 20A process is progressing towards volume production readiness as planned, while the Intel 18A process is scheduled to test production phase in the first quarter of next year.

Facing the strong competition from Samsung and Intel, TSMC is not sitting idle. According to reports citing from Financial Times, TSMC has showcased its 2nm prototype test results to major clients like Apple and NVIDIA.

TSMC previously mentioned in its earnings call that it expects the 2nm process to enter mass production as scheduled in 2025. The company’s 2nm backside power rail solution is scheduled for the latter half of 2025, with mass production slated for 2026.

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(Photo credit: ASML)

While TSMC makes promising strides in the 2nm process, slated for mass production in 2025, rivals Samsung and Intel are making headlines with aggressive moves to secure cost-effective deals. This surge in competition for the 2nm process is intensifying.

According to CNA, experts suggest that given the escalating rivalry in the AI chip market, it is paramount to have flawless execution in the process. Despite the recent efforts from Samsung and Intel, TSMC is anticipated to clinch the lion’s share of 2nm orders.

TSMC’s 2nm process is on track for mass production in 2025, with construction underway at its first 2nm fab in the Phase 2 Expansion Area of the Baoshan Site in the Hsinchu Science Park. The tool-in is scheduled for April next year. Simultaneously, TSMC’s Kaohsiung fab is earmarked as a crucial production base for 2nm in the future.

• [News] Samsung’s Discount Strategy Challenges TSMC as the Battle for 2nm Orders Heats Up

Samsung is gearing up for mass production of its 2nm process in 2025 as well. Reports from the Financial Times indicate that, in a bid to secure orders from industry giants like NVIDIA, Samsung is contemplating discounted offerings to challenge TSMC.

Intel, in its bid to reclaim its place in the semiconductor landscape, has set an big target of advancing 5 nodes in four years. Sanjay Natarajan, Senior Vice President at Intel, revealed in a recent interview with Nikkei Asia that the company aims to commence mass production of 2nm chips in 2024, with a commitment to providing reasonably priced products. Additionally, Intel’s 18A process is poised for trial production in the first quarter of 2024.

• [News] Intel, Samsung, TSMC Race in Cutting-Edge Processes

Analysts also share the insights of the competitive landscape among the three major semiconductor players, TSMC, Samsung, and Intel. Arisa Liu, the research fellow and director at the Taiwan Industry Economics Services of Taiwan Institute of Economic Research, notes that TSMC’s 2nm is expected to adopt a gate-all-around (GAA) architecture. In contrast, Samsung has taken an early lead by introducing GAA architecture in its 3nm, aiming to outpace TSMC in the 2nm process after 1 or 2 years of adjustments.

Liu highlights the challenges facing Samsung, noting that the 3nm GAA process has exhibited unstable yields. For example, Qualcomm, a major player in mobile chip, has reverted to TSMC for production. Even with Samsung’s plans for bidding at a reduced price, it is anticipated to face difficulties in denting TSMC’s order share in the short term.

Turning attention to Intel, Liu observes that Intel’s current process technology has advanced to Intel 4 and Intel 3, which do not align with the industry’s 4nm and 3nm processes. In reality, Intel’s progress is closer to 7nm or an enhanced version thereof. Notably, Intel’s 3nm products are still estimated to be outsourced to TSMC, signaling a substantial technology gap.

TSMC’s President, C.C. Wei, has previously outlined the company’s plan to initiate mass production of the 3nm N3P process in the latter half of 2024. Notably, its performance metrics, including power, performance, area (PPA), are expected to surpass Intel’s 18A.

Liu further pointed out the news of TSMC’s clients contemplating additional foundry partners has surfaced recently. This move is primarily seen as an attempt to exert pressure on TSMC and gain negotiating leverage. Given the fierce competition in the AI chip market, it is imperative to control precision in the manufacturing process. As such, TSMC’s 2nm is anticipated to secure a significant majority of orders.

(Image: TSMC)

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