Despite the uncertainties in the semiconductor market, there is still an intense global competition in the development of advanced semiconductor manufacturing processes. TSMC as one of the key players in the foundry industry is actively advancing its next-generation 2nm process. According to market rumors, the schedule for the first tool-in at Hsinchu Baoshan Fab and Kaohsiung Fab has been established, along with a finalized production capacity plan.

CNA has reported that TSMC’s 2nm process will be deployed in the Phase 2 Expansion Area of the Baoshan Site at the Hsinchu Science Park. The first tool-in is scheduled for April 2024. Industry sources have revealed that the initial production capacity for this process will be around 30,000 wafers per month, with mass production planned for the following year.

In addition, TSMC’s fab in Kaohsiung has notified equipment suppliers that this facility is set to begin in the third quarter of 2025. According to MoneyDJ, the pilot run is planned for the end of the same year, with the aim of achieving mass production in 2026. The Kaohsiung fab will adopt the N2P process, which is an enhanced version of the 2nm process with the backside power rail technology. The initial monthly production capacity is also expected to be around 30,000 wafers.

According to previous disclosures made by TSMC during financial calls, the company has developed a backside power rail solution for the N2 process, which is particularly suitable for high-performance computing (HPC) applications. This innovative technology is expected to boost speed by 10% to 12% and increase logic density by 10% to 15%. TSMC plans to introduce the backside power rail solution to customers in the latter half of 2025, with mass production scheduled for 2026. This timetable aligns with recent rumor circulating in the supply chain.

In addition to the latest progress on the N2P process, TSMC made an official announcement at the IEEE International Electron Devices Meeting (IEDM) on December 12th. Specifically, the company revealed its plans to introduce a 1.4nm process as the successor to the 2nm process. As reported by Tom’s Hardware, this new process, named A14, continues the naming convention from the 2nm process (A20). Production using the A14 process is anticipated to take place between 2027 and 2028.

(Image: TSMC)

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Both TSMC and Samsung plan to start production on the 2nm process in 2025, triggering an early battle for related orders. According to sources reported by the Financial Times (FT), Qualcomm intends to shift production of its next-generation high-end mobile chips from TSMC to Samsung’s 2nm process. Samsung, offering substantial discounts, is aggressively pursuing orders from major players like NVIDIA, posing a challenge to TSMC’s dominance.

According to reports citing insider information, TSMC has showcased its 2nm prototype test results to major clients like Apple and NVIDIA. Additionally, sources indicate that Samsung is not only planning to introduce its 2nm prototype but is also offering discounted prices, attracting interest from prominent clients, including NVIDIA.

The report highlights that Qualcomm is planning to use Samsung’s “SF2” (2nm) process for the next generation of high-end smartphone chips. Samsung, as the first company to globally mass-produce 3nm (SF3) chips last year, is also the pioneer in adopting the new Gate-All-Around (GAA) transistor architecture.

Samsung indicated that, “We have fully deployed and can mass-produce SF2 in 2025. Since we are the first company to enter and transform the GAA architecture, we hope that the progress from SF3 to SF2 will be relatively smooth.”

However, insiders have disclosed that Samsung’s yield for the most basic 3nm chips is only 60%, significantly below customer expectations. Moreover, when producing chips with complexity equivalent to Apple’s A17 Pro or NVIDIA graphics processing units (GPUs), the yield may further decrease.

Global giants such as Qualcomm and NVIDIA follow a diversified wafer foundry strategy, but they still rely heavily on TSMC for now. Previously, NVIDIA’s Chief Financial Officer, Colette Kress, hinted during the UBS Global Technology Conference that NVIDIA may consider Intel for the production of its next-generation chips, potentially breaking away from the exclusive partnership with TSMC for AI chips.

Now, Qualcomm is also exploring collaboration with Samsung for the 2nm process, intensifying the pressure on TSMC to address potential order losses from two major clients in advanced semiconductor manufacturing.

TSMC, on the other hand, informed the Financial Times that the development progress of its 2nm process is proceeding smoothly, and it is scheduled for production in 2025. When launched, it will represent the industry’s most advanced semiconductor technology in terms of density and energy efficiency.

In a previous investor conference, TSMC stated that there is significant customer interest and engagement in 2nm for high-speed computing and smartphone applications. It is expected that 2nm, when introduced in 2025, will be the most advanced semiconductor technology in the industry, comparable or even superior to 3nm at the same stage.

TSMC plans to launch the 2nm backside power rail solution in the second half of 2025, with mass production scheduled for 2026.

Besides TSMC and Samsung actively advancing towards 2nm and more advanced processes, Intel has also joined the competition. The Financial Times characterizes this race for the 2nm process as “shaping the future of a USD 500 billion industry.”

Intel is progressing along its previously set 5 process nodes in a four-year trajectory. The Intel 4 process is ready for mass production, and the Intel 3 process is planned for launch later this year. Intel CEO, Pat Gelsinger, has previously showcased the Intel 20A wafer, which is expected to enter the pre-production phase in the first half of next year. The Intel 18A process is scheduled for mass production in the second half of 2024.

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(Photo credit: Samsung)

Equipment is playing an indispensable role during the wafer manufacturing process. In response to market needs, the global EUV lithography supplier, ASML, has recently taken significant steps.

ASML’s Bold Move: Annual Investment of EUR 100 Million in Berlin Plant

As reported by the German media “Handelsblatt,” the Netherlands-based company ASML plans to invest EUR 100 million (USD 109 million) in 2023, with a similar annual investment in the subsequent years. This investment aims to enhance the production and development capabilities of ASML’s manufacturing plant located in Berlin, Germany.

Reports indicate that ASML’s Berlin plant primarily produced core components of EUV equipment, including wafer clamps, wafer tables, reticle chucks and mirror blocks. ASML acquired this facility, known as “Berliner Glas,” in 2020.

Foundries Actively Pursue EUV equipment

The EUV equipment plays a crucial role in manufacturing, utilizing specific wavelength light for radiation to precisely imprint images on wafers. Currently, the EUV equipment market is highly concentrated, with only a few global companies mastering this technology. Among them, Dutch company ASML stands out as the world’s largest and most advanced EUV company. Additionally, companies like Nikon, Canon, and Shanghai Micro Electronics Equipment (SMEE) are strategically positioning themselves in the EUV sector.

EUV technology, used for exposing semiconductor process, is indispensable due to its high cost, complex processes, and limited supply. ASML is the sole global supplier of EUV. For advanced processes below 7nm, EUV serves as an essential device. Developed over more than 20 years, EUV technology has become the cornerstone of advanced processes, enabling the continuation of Moore’s Law for at least another decade.

As a crucial EUV equipment supplier, ASML is working on a new generation of NA-EUV equipment, where “NA” represents numerical aperture. A higher NA value means a higher achievable resolution, allowing for more transistors on the chip. It is expected that by the year-end, ASML will unveil the world’s first high-NA EUV and deliver it to Intel.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

TSMC’s 2nm process will continue to leverage EUV technology. In a previous announcement in September, TSMC disclosed the acquisition of Intel’s subsidiary IMS for up to US 432.8 million, focusing on the research and production of electron beam lithography machines. Industry experts believe that TSMC’s move ensures the technical development of critical equipment and meets the supply demand for the commercialization of 2nm.

Following 2nm chips. Samsung plans to achieve mass production of 2nm processes in the mobile field by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively. According to the report in September, Samsung is gearing up to secure the yield of the next-generation EUV equipment, High-NA, with the prototype expected to launch later this year and official supply next year.

After announcing its return to the foundry business, Intel revealed in October that it has commenced mass production of Intel 4 process nodes using EUV technology. Currently, both Intel 7 and Intel 4 have achieved mass production, and Intel 3 is progressing according to plan, with the goal of completion by the end of 2023.

(Image: ASML)

The growing importance of advanced processes in wafer foundries is evident, propelled by innovations like AI and high-performance computing. While 3nm chips have entered the consumer market, efforts are underway in wafer foundries to advance to 2nm chips. Recent reports suggest progress in 1nm chips, further fueling the competition among wafer foundries.

2nm Chips: Unveiling in 2025

Anticipated by 2025, the race for 2nm chips is in full swing, with major players like TSMC, Samsung, and Rapidus actively pursuing mass production. TSMC plans to implement GAAFET transistors in its 2nm process by 2025, offering a 15% speed boost and up to a 30% reduction in power consumption compared to N3E, all while increasing chip density by over 15%.

Samsung is on a similar trajectory, planning to unveil its 2nm process by the end of 2025. As report by media in October, Samsung Foundry, said on Semiconductor Expo 2023 in South Korea, has already initiated discussions with major clients, expecting decisions in upcoming future.

Rapidus aims for trial production of 2nm chips in 2025, scaling up to mass production by 2027. Reports in September indicated that ASML plans to establish a technical support hub in Hokkaido, Japan in 2024. Approximately 50 engineers will be dispatched to Rapidus’ ongoing construction site for the 2nm plant, assisting in the setup of EUV lithography equipment on the trial production line, and providing support for factory activation, maintenance, and inspections.

When will 1nm chip arrive?

Apart from 2nm, the industry’s attention turns to 1nm-level chips. According to industry plans, mass production of 1nm-level chips is expected between 2027 and 2030.

Nikkei recently reveals collaboration between Japanese chipmaker Rapidus, Tokyo University, and the French technological research organization Leti to develop foundational technology for 1nm IC design. Talent exchange and technical sharing are slated to begin in 2024, aiming to establish a supply system for indispensable 1nm chip products, crucial for enhancing auto driving and AI performance.

On the other hand, collaborations with IBM for 1nm products are also being considered. The computing performance of 1nm products, anticipated to become mainstream in the 2030s, is expected to surpass 2nm by 10-20%.

TSMC and Samsung are also eyeing 1nm chip development. TSMC’s initial plan to build a 1.4nm process wafer fab in Taiwan faced delays after abandoning the original site selection in October. Samsung aims to launch its 1.4nm process by the end of 2027, with improved performance and power consumption through an increased number of nanosheets per transistor, promising enhanced control over current flow and reduced power leakage.

(Image: TSMC)

According to TechNews’ report, Gitae Jeong, Vice President of Samsung Electronics, recently revealed in an interview that the company is set to introduce the SF1.4 (1.4nm) process, expected to enter mass production in 2027.

This announcement intensifies the competition in advanced semiconductor manufacturing, particularly in the development of 2.5D/3D integrated heterogeneous structure packaging among the three major semiconductor foundry giants.

• TSMC: N3P Process Superior to Intel 18A, N2 to Lead Industry’s Advanced Processes

Previously, the semiconductor industry reported challenges with both TSMC and Samsung achieving yields above 60% for their 3nm processes due to undisclosed issues. TSMC’s yield was reported to be only 55%, below the normal yield rate.

However, TSMC’s President, C.C. Wei, expressed optimism, stating that current N3 demand is better than three months ago, contributing to a healthy growth outlook for TSMC in 2024.

Wei also anticipates that TSMC’s 3nm process will contribute a mid-single-digit percentage (4%-6%) to the company’s annual wafer revenue in 2023.

Regarding competition with rival Intel’s 18A process, Wei believes that TSMC’s N3P process offers better performance, power, and area (PPA), alongside improved cost efficiency and technical maturity. Furthermore, TSMC’s upcoming N2 process is expected to be the industry’s most advanced when introduced.

• Intel: Striving for the Fourth Customer for 18A Process Outsourcing Orders

Intel’s CEO, Pat Gelsinger, has revealed that the 18A process has secured orders from three customers and aims to acquire a fourth customer by the end of the year. The advanced 18A process is scheduled to begin production at the end of 2024, with one customer already having made an advance payment. External expectations suggest that the customer could possibly be NVIDIA or Qualcomm.

Intel has stated that Intel 4 and Intel 3 processes are similar, as are Intel 20A and Intel 18A processes. Consequently, Intel’s primary focus will be on offering Intel 3 and Intel 18A to semiconductor foundry customers. Meanwhile, Intel 4 and Intel 20A processes are more likely to be used internally. However, Intel is open to accommodating customer requests if they express interest in adopting these later processes.

• Samsung: Commencing Mass Production of SF2 in 2025, Prioritizing Internal Use

Due to challenges with the three-nanometer (3nm) manufacturing process, there have been reports that Samsung plans to shift directly to the more advanced two-nanometer (2nm) process.

According to Samsung’s Foundry Forum (SFF) plan, they will begin mass production of the 2nm process (SF2) in 2025 for mobile applications, expand to high-performance computing (HPC) applications in 2026, and further extend to the automotive sector and the expected 1.4nm process by 2027.

Similar to Intel, Samsung intends to prioritize the production of its own products using the 2nm process. The 2nm process products will initially be utilized for Samsung’s in-house products rather than external customer products.

• Summary

While TSMC’s N3 series currently enjoys broad support, including N3E, N3X, and N3P process series, the move to 2nm introduces new variables as it adopts a completely new GAAFET architecture. Regardless, whether it’s TSMC’s N2, Intel’s 18A, or Samsung’s SF2, each of them possesses its competitive strengths. The industry is also eagerly anticipating the future developments in advanced semiconductor processes.

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