In the memory sector, the era beyond 10nm seems to be around the corner, as giants have revealed plans on the production of 1c DRAM. SK hynix, according to a report by The Elec, is said to develop a 4F2 (square) DRAM in order to reduce the high cost associated with the extreme ultraviolet (EUV) processes since the commercialization of 1c DRAM.

During an industry conference on Monday, Seo Jae Wook, a SK hynix researcher, questioned the profitability of producing DRAM with EUV technology. Instead, he said that SK hynix is exploring the possibility of manufacturing future DRAMs using vertical gate (VG) or 3D DRAM structure, according to the report.

Sources cited by the report indicate that Samsung and SK hynix are both targeting to apply 4F2 for DRAM at the 10nm node and beyond. According to Seo, by applying VG or the 3D DRAM structure, the cost of the EUV processes can be reduced by half.

SK hynix’s VG, or the so-called 4F2 by memory makers internally, is similar to the vertical channel transistor (VCT) of its South Korean competitor Samsung, The Elec explains.

In short, unlike the traditional 2D DRAM, which only uses the horizontal plane, 4F2, or 3D DRAM, is a cell array structure where transistors are stacked vertically. In the structure, various parts including the source, gate, drain, and capacitor are stacked from bottom to top. As the word line connects to the gate, the bit line connects to the source.

According to the report, arranging the cell array in this manner can reduce the die surface area by 30% compared to 6F2 DRAM.

However, according to a previous report by TweakTown, though the 4F2 design possesses the advantages of being compact and power-efficient, its complexity demands extreme precision in fabrication, higher-quality materials for production, and extensive research to make it scalable and suitable for mass production.

According to TweakTown, Samsung is anticipated to finalize the initial development of VCT DRAM by 2025, with 3D DRAM expected to enter the market by 2030.

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(Photo credit: SK hynix)

According to a report by Korean media outlet Business Korea, SK Hynix recently shared its latest breakthrough on its 3D DRAM at VLSI 2024 last week, announcing that the manufacturing yield of its 5-layer stacked 3D DRAM has reached 56.1%.

This means that out of roughly 1,000 3D DRAM units manufactured on a single test wafer, about 561 functional devices were successfully manufactured, the report further explains. The experimental 3D DRAM exhibits characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix has disclosed specific numbers and characteristics of its 3D DRAM development.

However, SK Hynix also noted that while 3D DRAM holds great potential, a significant amount of development is still required before it can be commercialized. The memory giant also reportedly pointed out that unlike the stable operation of 2D DRAM, 3D DRAM exhibits unstable performance characteristics, and stacking 32 to 192 layers of memory cells is necessary for widespread use.

3D DRAM is also a key development area for other major memory manufacturers like Samsung Electronics and Micron. Samsung Electronics has successfully stacked 3D DRAM up to 16 layers and plans to mass-produce 3D DRAM around 2030. Micron currently holds 30 patents related to 3D DRAM, and if there are breakthroughs in 3D DRAM technology, it could produce better DRAM products than existing ones without the need for EUV equipment.

The DRAM market remains highly concentrated, currently dominated by key players such as Samsung Electronics, SK Hynix, and Micron Technology, collectively holding over 96% of the entire market share.

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(Photo credit: SK Hynix)