Kioxia is set to introduce its progress on DRAM storage-class memory (SCM) and 3D-NAND technologies at the IEEE International Electron Devices Meeting (IEDM) 2024 conference in San Francisco in December, featuring its Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) technology jointly developed with Taiwan memory chipmaker Nanya Technology, as well as MRAM-based storage-class memory jointly developed with SK hynix, according to a report from Block and Files.

Kioxia will reportedly present a new type of DRAM with oxide semiconductors that reduce power consumption, MRAM suitable for larger capacities for SCM applications, and a new 3D NAND structure with superior bit density and performance.

According to the report, Kioxia has developed the DRAM with oxide semiconductors with Nanya Technology. This Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) features a gate-all-round InGaZnO (Indium Gallium Zinc Oxide) vertical transistor with the oxide that can reduce current leakage to an “extremely low” level. According to Kioxia’s press release, the technology has the potential to reduce power consumption across various applications, such as AI, post-5G communication systems, and IoT devices.

The MRAM-based storage-class memory is developed with SK hynix. According to Kioxia’s press release, the companies have achieved cell read/write operation at the smallest-ever scale of cell half-pitch of 20.5 nanometers for MRAM. The press release pointed out that memory reliability tends to degrade as cells are miniaturized. The companies develop a new read/write method that can reduce the unwanted capacitance that occurs in the readout circuits.  According to Kioxia’s press release, this technology has practical applications for AI and big data processing.

Last, Kioxia developed a new 3D NAND structure, aiming to enhance reliability and prevent the performance degradation of NAND-type cell. In conventional structures, degradation of performance typically occurs when the number of stacked layers increases. Compared to the conventional structure that stacks NAND-type cells vertically, the new structure arranges NAND-type cells horizontally. The press release indicated that this new structure makes it possible to develop 3D flash memory with high bit density and reliability at low cost.

(Photo credit: Kioxia)

According to a previous report from Bloomberg, Chinese 3D NAND Flash giant YMTC recently filed a lawsuit against American memory giant Micron in California, accusing Micron of infringing on 11 of its patents related to 3D NAND Flash and DRAM products. YMTC is requesting the court to order Micron to stop selling the infringing memory products in the United States and to pay patent royalties.

Established at the end of 2016 in Wuhan, YMTC is a major Chinese manufacturer of memory (DRAM) and flash memory (NAND Flash), supported by significant investments from the “Big Fund.” It has become a representative enterprise in China’s effort to build a local chip supply chain. However, in October 2022, the U.S. Department of Commerce added YMTC to the Entity List, preventing it from obtaining advanced equipment from U.S. companies to manufacture 3D NAND chips with 128 layers or more.

Before facing U.S. export controls, YMTC’s 128-layer 3D NAND chip products had already entered Apple’s supply chain and received technical and quality certification from Apple. At that time, Apple reportedly hoped to use YMTC’s chips not only for cost considerations but also to prevent flash memory from being overly concentrated in the hands of Samsung, SK Hynix, and Micron.

The report from Tom’s hardware states that YMTC’s current allegations assert that Micron’s 96-layer (B27A), 128-layer (B37R), 176-layer (B47R), and 232-layer (B58R) 3D NAND Flash products, as well as some DDR5 SDRAM products (Y2BM series), infringe on 11 of YMTC’s patents or patent applications filed in the United States.

Notably, last November, YMTC also filed a lawsuit against Micron and its subsidiaries in the U.S. District Court for the Northern District of California, accusing them of infringing on eight U.S. patents related to 3D NAND Flash. Additionally, per a report from South China Morning Post on June 7th of this year, YMTC filed a lawsuit in California, accusing the Denmark-based consulting firm Strand Consult, funded by Micron, of spreading false information that damaged YMTC’s market reputation and business relationships.

Industry sources cited by the Commercial Times also note that in recent years, China’s technological capabilities have significantly improved, and companies have been actively applying for patents domestically and internationally. With the support of the Chinese government, they have also started to frequently engage in patent litigation. Last year, Chinese courts received 5,062 technical intellectual property and monopoly cases.

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(Photo credit: YMTC)

After ending production cuts amidst a recovery in the memory industry, Kioxia disclosed its plans on the 3D NAND roadmap last week. According to reports from PC Watch and Blocks & Files, Kioxia stated that achieving a 1,000-layer level by 2027 would be possible.

According to the reports, the number of 3D NAND layers has generally increased from 24 in 2014 to 238 in 2022, representing a tenfold rise over eight years. Kioxia stated that achieving a 1,000-layer level by 2027 would be possible at a rate of increase of 1.33 times per year.

The Japanese memory chipmaker seems to be more ambitious than Samsung regarding the battle of layers. In May, Samsung revealed its target to release advanced NAND chips with over 1000 layers by 2030. According to Wccftech, the South Korean memory giant plans to apply new ferroelectric materials on the manufacturing of NAND to achieve this goal.

According to the latest analysis from TrendForce, Kioxia has benefited from the recovery of the memory industry, recently receiving subsidies from the Japanese government and additional financing from a consortium of banks. Furthermore, the company plans to launch an IPO by the end of the year. These measures have provided Kioxia with ample financial resources to pursue technological advancements and cost optimization.

TrendForce further notes that Kioxia has ambitious plans to achieve 1000-layer technology by 2027, which is the highest number of layers announced by any manufacturer so far. However, to reach the milestone, it will be necessary to transition from TLC (3 bits per cell) to QLC (4 bits per cell), and possibly even to PLC (5 bits per cell). The technical challenges involved are significant, and whether Kioxia can achieve this market milestone by 2027 remains to be seen.

The Battle of Layers between Memory Giants

Kioxia and its partner Western Digital showcased their 218-layer technology in 2023 following the 162-layer milestone. Its current announcement to achieve the 1000-layer technology by 2027 would be a huge leap from that.

The battle of layers between memory giants has been intensifying as other memory heavyweights had already surpassed the 200-layer milestone. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290, according an earlier report by The Korea Economic Daily. For now, the company aims to stack V-NAND to over 1000 layers by 2030.

SK Hynix unveiled the world’s highest-layer 321-layer NAND flash memory samples in August 2023, claiming to have become the industry’s first company developing NAND flash memory with over 300 layers, with plans for mass production by 2025. Micron has also started to mass produce its 232-layer QLC NANDs in 2024.

Uncertainties behind Kioxia’s Optimism

However, to Kioxia, there are more challenges to overcome, as technological obstacles and Western Digital’s stance add uncertainties to its ambition. According to the report from Blocks & Files, increasing density in a 3D NAND die involves more than just adding layers, as each layer’s edge must be exposed for memory cell electrical connectivity. This results in a staircase-like profile, and as the number of layers grows, the die area needed for the staircase expands as well.

Therefore, to increase density, it is necessary to shrink the cell size both vertically and laterally, and to raise the bit level as well. All these scaling factors, including layer counts, vertical cell size reduction, lateral cell size reduction, and cell bit level increases, present their own technological challenges.

Moreover, according to Blocks & Files, WD has concerns regarding the manufacturing capital costs and the return on investment from selling chips and SSDs made with the fabricated NAND dies.

Citing Western Digital EVP Robert Soderbery in June, the report noted that in the 3D era, NAND manufacturing requires higher capital intensity but offers a lower cost reduction as bit density increases. The company even described the situation as the “end of the layers race,” indicating that there would be a slowdown in the rate of NAND layer count increases to optimize capital deployment.

How long would the battle of layers continue, and how far would it go? Technological breakthroughs as well as the willingness to endure higher capital intensity while the cost reduction being relatively limited may be key.

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(Photo credit: Kioxia)

As the leading global supplier of NAND memory, Samsung is embarking on an ambitious journey to enhance its V-NAND technology, also known as 3D NAND. Early in this week, Samsung has officially declared its commitment to commence mass production of the 9th generation V-NAND memory, featuring an astonishing 300+ layers, by 2024. This achievement will establish a new industry record for the highest number of active layers, solidifying Samsung’s industry leadership.

In a blog post on Samsung Electronics, Jung-Bae Lee, President and Head of Samsung Electronics’ Memory Business, stated, “The ninth-generation V-NAND is well under way for mass production early next year with the industry’s highest layer count based on a double-stack structure.”

Samsung was diligently working on the 9th generation V-NAND back in August this year, preserving the double-stacked technology they first introduced in 2020. Not only is Samsung confirming the trajectory of their next-gen non-volatile memory technology, but it also surpasses competitors by boasting more active layers. It’s been disclosed that SK Hynix’s upcoming 3D NAND will have 321 active layers, Samsung is set to surpass this number.

Jung-Bae Lee further elaborated, “Samsung is also working on the next generation of value-creating technologies, including a new structure that maximizes V-NAND’s input/output (I/O) speed.”

While precise performance details of Samsung’s 9th generation V-NAND remain undisclosed, it will power their upcoming SSDs. In the near future, it is anticipated that Samsung will introduce retail SSDs with the PCIe Gen5 interface, in line with the Samsung 990 Pro series.

Regarding long-term technological advancement, Samsung is committed to minimizing interference between units, reducing device dimensions, and maximizing the count of vertical layers. These innovative strides are clearing the path for Samsung to achieve the industry’s most compact unit size. These endeavors will propel Samsung toward their ambitious goal of developing over 1,000 layers of 3D NAND and distinctive memory solutions, ensuring the continued relevance of their products for data centers, personal computers, and a wide range of applications.

(Image: Samsung)

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