Global semiconductor giants are concentrating their R&D efforts on advanced packaging technologies to drive performance enhancements. According to a report from Commercial Times, as packaging technology progresses from 2.5D to 3D, chip stacking technologies have become a showcase for the competitive prowess of major companies.

“Hybrid Bonding” is seen as the key technology for future chip connections. In addition to international companies like Applied Materials and Besi actively positioning themselves, Taiwanese companies led by TSMC, including Gallant Micro, MPI Corporation, E&R Engineering Corporation, C SUN, Saultech, and Grand Process Technology, are also developing and seizing opportunities in Hybrid Bonding.

The report also cited industry sources, pointing out that Grand Process Technology has been supplying TSMC since the inception of InFO (Integrated Fan-Out Packaging). It is revealed that Grand Process Technology is also actively participating in future SoIC (System on Integrated Chips) advanced packaging, focusing on wafer cleaning and photoresist removal in etching processes.

It is indicated by the report that Grand Process Technology’s capacity will be operating at full speed until the first quarter of next year, with lead times extended to nine months. Last year’s orders are currently being installed gradually, with most concentrated on advanced packaging.

Semiconductor equipment manufacturer C SUN and its investment company Gallant Micro are currently investing in Hybrid Bonding-related equipment. C SUN primarily focuses on developing the best solutions for permanent bonding to enhance yield rates. Meanwhile, Gallant Micro leverages its relative advantage in chip sorting machines within its product line.

MPI Corporation, a testing interface vendor, has also entered the initial stages of inspection and analysis for Hybrid Bonding processes. Development of related products is nearing completion.

E&R Engineering Corporation also emphasizes that its top-tier plasma cleaning equipment is currently aimed at achieving high cleanliness of bonding surfaces to enhance adhesion.

Saultech Technology holds a positive outlook on the future market trends of Hybrid Bonding as well. The company has introduced equipment that corresponds to both Hybrid Bonding and Fan-Out technologies. Saultech has independently developed key technologies including bonding and die cleaning processes.

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(Photo credit: Applied Materials)

In 2023, Samsung disclosed plans to launch its advanced three-dimensional (3D) chip packaging technology, which would be able to integrate memory and processors needed for high-performance chips, in much smaller sizes. Now, at the Samsung Foundry Forum in San Jose taken place in June, the tech giant made it public that it would introduce 3D packaging services for HBM within this year, according to the latest report by The Korea Economic Daily.

For now, HBM chips are predominantly packaged with 2.5D technology. Citing industry sources as well as personnel from Samsung, the company’s 3D chip packaging technology is expected to hit the market for HBM4, the sixth generation of the HBM family.

Samsung’s announcement regarding its 3D HBM packaing roadmap has been made after NVIDIA CEO Jensen Huang revealed Rubin at COMPUTEX 2024, the company’s upcoming architecture of its AI platform after Blackwell. The Rubin GPU will reportedly feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, targeting to be released in 2026.

Currently, Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs, while SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D, on the other hand, entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

The Korea Economic Daily noted that unlike 2.5D technology, under which HBM chips are horizontally connected with a GPU on a silicon interposer, by stacking HBM chips vertically on top of a GPU, 3D packaging could further accelerate data learning and inference processing, and thus does not require a silicon interposer, a thin substrate that sits between chips to allow them to communicate and work together.

It is also understood that Samsung plans to offer 3D HBM packaging on a turnkey basis, according to the Korea Economic Daily. To achieve this, its advanced packaging team will vertically interconnect HBM chips produced by its memory business division, with GPUs assembled for fabless companies by its foundry unit, the report noted.

Regarding Samsung’s long-time rival, TSMC, the company’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and HBM stacks side by side on one interposer. TSMC also made similar announcement in May, reportedly utilizing 12nm and 5nm process nodes in manufacturing HBM4, according to a report by AnandTech.

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• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process
• [News] Samsung Accelerates 3D Packaging with Hybrid Bonding Production Line in Korean Advanced Packaging Hub

(Photo credit: Samsung)

The semiconductor industry enters the era of integration. Various foundries are focusing on advanced packaging technologies, but the terminology surrounding advanced packaging can be daunting. This article aims to explain these terms in the simplest way possible.

According to a report from TechNews, currently, there are two main trends in advanced packaging: heterogeneous integration and chiplets.

In fact, the concept of “heterogeneous integration” has been developing for many years and is not exclusive to advanced packaging. It is not only used for the integration of heterogeneous chiplets but also for integrating other non-chip active/passive components into a single package, which is the technology commonly used in traditional Outsourced Semiconductor Assembly and Test Services(OSATs).

• Heterogeneous Integration = Big Building Blocks? Advanced Packaging = Small Building Blocks? 

In the simplest terms, “heterogeneous integration” can be likened to building with large building blocks, while “advanced packaging” is akin to assembling with small building blocks. Some manufacturers, like traditional Outsourced Semiconductor Assembly and Test Services(OSATs), excel in stacking large blocks, such as logic circuits, radio frequency circuits, MEMS (Micro-Electro-Mechanical Systems), or sensors, onto a IC substrate. The stacking of these different large blocks represents the concept of heterogeneous integration.

On the other hand, some blocks are too small to stack effectively, requiring assistance from advanced packaging, typically provided by semiconductor foundries.

Advanced packaging also encompasses 2.5D packaging and 3D packaging. Using the metaphor of building blocks, the former involves horizontally stacking small building blocks on a interposer, while the latter involves vertically stacking small building blocks with interconnection facilitated through Through-Silicon Vias (TSVs), which are ultra-small building blocks.

It’s important to emphasize that stacking blocks is a conceptual representation, and the distinction between large and small blocks is relative. The analogy above refers to heterogeneous integration in traditional packaging, and heterogeneous integration in advanced packaging follows a similar concept, but with even smaller building blocks.

• SoC / SiP / Heterogeneous Integration / Chiplet

With this concept in mind, let’s discuss the applications of heterogeneous integration in advanced packaging:

Among the various packaging types, SoC (System On Chip) involves integrating different chips such as processors and memory, with different functions, redesigned and fabricated using the “same process,” integrated onto a single chip, resulting in a final product with only one chip.

On the other hand, SiP (System in Package) involves connecting multiple chips with “different processes” through “heterogeneous integration” technology, integrated within the same packaging module. Therefore, the final product will be a system with many chips on it, resembling the stacking of different-sized building blocks mentioned earlier.

Therefore, heterogeneous integration refers to integrating different and separately manufactured components (heterogeneous) into higher-level assemblies. These components include blocks of different sizes, such as MEMS devices, passive components, logic chips, and more.

However, at a certain point, for the sake of process development, researchers found that separating components at the right time might facilitate miniaturization. Hence, chiplet was born.

• Is Chiplet the Fusion of Heterogeneous Integration and Advanced Processes?

As demands for ICs become increasingly complex, the size of SoC chips continues to grow. However, cramming too many components onto a limited substrate poses significant challenges, including heightened process complexity and reduced yield.

Hence, the concept of chiplets emerged, advocating for the segmentation of SoC functionalities, such as data storage, computation, signal processing, and data flow management, into smaller individual chips. These chiplets are then integrated through packaging to form a interconnected network.

It’s worth noting that Chiplets are essentially chips, whereas SiP refers to the packaging format. Chiplet architecture enable the reduction of individual chip sizes, simplify circuit design, overcome manufacturing difficulties and yield issues, and offer greater design flexibility.

• Advanced Packaging Technologies in Foundries

Currently, advanced packaging can be broadly categorized into three main types: Wafer-Level Packaging (WLP), 2.5D Packaging, and 3D Packaging. Traditional packaging involves cutting wafers into chips before packaging, while advanced packaging entails packaging the silicon wafer before cutting, requiring subsequent stacking processes in fabs. Therefore, the technology is primarily the responsibility of fabs.

Traditional packaging involves cutting wafers into chips before packaging. Advanced packaging, starting from wafer-level packaging, involves packaging silicon wafers before cutting, and subsequent stacking requires wafer fabrication processes.

Therefore, this article will delve into advanced packaging technologies offered by the three major foundries, with a focus on 2.5D and 3D packaging.

• 2.5DIC / 3DIC Packaging

To further explain using building blocks, the difference between 2.5D and 3DIC packaging lies in the “stacking method.”

In 2.5D packaging, processors, memory, or other chips are stacked horizontally on a silicon interposer using a flip-chip method, with micro bumps connecting different chip’s electronic signals. Through silicon vias (TSVs) in the interposer link to the metal bumps below, then packaged onto the IC substrate, creating tighter interconnections between the chips and the substrate.

In a side view, although the chips are stacked, the essence remains horizontal packaging, with the chips positioned closer together and allowing for smaller chip sizes. Additionally, this is a form of “heterogeneous integration” technology.

3D packaging involves stacking multiple chips (face down) together, directly using through-silicon vias to stack them vertically, linking the electronic signals of different chips above and below, achieving true vertical packaging. Currently, more and more CPUs, GPUs, and memories are starting to adopt 3D packaging technology.

• Hybrid Bonding

Hybrid bonding is one of the die bonding techniques used in advanced chip packaging processes. One of the commercially available technologies in this domain is the “Cu-Cu hybrid bonding.”

In traditional wafer bonding processes, there are interfaces between copper and dielectric materials. With “Cu-Cu hybrid bonding,” metal contacts are embedded within the dielectric material. Through a thermal treatment process, these two materials are bonded together, utilizing the atomic diffusion of copper metal in its solid-state to achieve the bond. This approach addresses challenges encountered in previous flip-chip bonding process.

Compared to flip-chip bonding, hybrid bonding offers several advantages. It allows for achieving ultra-high I/O counts and longer interconnect lengths. By using dielectric material for bonding instead of bottom fillers, the cost of filling is eliminated.

Additionally, hybrid bonding results in minimal thickness compared to chip-on-wafer bonding. This is particularly beneficial for future developments in 3D packaging, where stacking multiple layers of chips is required, as hybrid bonding can significantly reduce the overall thickness.

• Advanced Packaging Moves Towards the Era of Heterogeneous Integration

As the semiconductor industry enters the “post-Moore’s Law era,” the development focus of advanced packaging is gradually shifting from 2D planar structures to 3D stacking and from single-chip designs to multi-chip configurations. Therefore, “heterogeneous integration” will play a crucial role in future advanced packaging.

Currently, prominent companies such as TSMC, Samsung, and Intel are intensifying their research and development efforts and capacity expansions in this field, introducing their innovative packaging solutions.

With ongoing technological advancements and innovations, advanced packaging and heterogeneous integration will play increasingly vital roles in propelling the semiconductor industry towards greater heights, meeting the complex and diverse demands of future electronic devices.

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(Photo credit: Intel)

As semiconductor manufacturing processes evolve more gradually, 3D packaging emerges as an effective means of prolonging Moore’s Law and enhancing the computational prowess of ICs. Within the realm of 3D stacking technology, the Interuniversity Microelectronics Centre (imec) based in Belgium categorizes 3D integration technologies into four distinct types, each determined by different partitioning locations within a chip: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC. Based on our previous discussion of 3D-SIP and 3D-SIC stacking, this article places a spotlight on the other two technologies: 3D-SOC and 3D-IC.

Related Article: Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

3D-SOC

A System on Chip (SOC) involves the redesign of several different chips, all fabricated using the same manufacturing process, and integrates them onto a single chip. 3D-SOC takes this concept to new heights by stacking multiple SOC chips vertically. The image below illustrates the transformation of a 2D System on Chip (2D-SOC), where circuits are redivided into blocks, and then stacked to form a 3D System on Chip (3D-SOC).

Source: imec

imec’s research team previously published a paper on IEEE, outlining the advantages of 3D-SOC and backside interconnects. This technology aims to achieve the integration of diverse chips in a heterogeneous system. By intelligently partitioning circuits, it significantly reduces power consumption and boosts computational performance. In comparison to the trending chiplet technology, 3D-SOC holds a competitive edge.

Eric Beyne, IMEC’s Vice President of Research and Project Director for 3D System Integration, pointed out, “Chiplets involve separately designed and processed chiplet dies. A well-known example are high-bandwidth memories (HBMs) – stacks of dynamic random access memory (DRAM) chips. This memory stack connects to a processor chip through interface buses, which limit their use to latency-tolerant applications. As such, the chiplet concept will never allow for fast access between logic and first and intermediate level cache memories.”

However, it’s essential to acknowledge that 3D-SOC technology comes with apparent drawbacks, primarily higher research and development costs and a longer development timeline compared to 3D-SIP technology. Nevertheless, as applications like AIGC, AR/VR, 8K, and others continue to drive the need for high-speed computing, chips are relentlessly progressing towards higher efficiency, lower power consumption, and smaller size. In this context, 3D-SOC technology will maintain its place in advanced packaging.

Backside Power Delivery Network (BSPDN)

The technology of Backside Power Delivery Network (BSPDN) represents a pivotal development in semiconductor manufacturing, offering several advantages, including more flexible circuit design, shorter metal wire lengths, and higher chip utilization. After transforming a 2D System on Chip (2D-SOC) into a 3D-SOC through layered stacking, the original back sides of the chips become the outer sides of the 3D-SOC. At this stage, the “freed-up” backside of the chips can be utilized for signal routing or as power lines for transistors, in contrast to traditional processes where wiring and power lines are designed on the front side of the wafer.

In the past, backside chips were merely used as carriers, but BSPDN technology allows for more space to be used for logic wafer design. According to simulation results, the transmission efficiency of backside PDN is seven times higher than traditional front-side PDN. Intel has also announced the introduction of this technology in the 20Å and 18Å processes.

To achieve BSPDN, a dedicated wafer thinning process (reducing it to a few hundred nanometers) is required, along with nanoscale through-silicon vias (nTSV) to connect backside power to the front-side logic chip.

Another key technology for BSPDN is the Buried Power Rail (BPR), a miniaturization technique that embeds wires beneath the transistors, with some inside the silicon substrate and others in shallow trench isolation oxide layers. BPR replaces power lines and ground lines under standard cells in traditional processes and further reduces the width of standard cells, mitigating IR voltage drop issues.

The diagram below illustrates BSPDN, where backside PDN’s metal wiring is connected to Buried Power Rails (BPR), and the backside of the chip (BS) is connected to the front side of the logic chip (FS).

Source: imec

3D-IC

The final category, 3D-IC, employs new 3D sequential technology (S3D) or Monolithic technology to vertically stack n-type and p-type transistors, forming a Complementary Field-Effect Transistor (CFET). This technology enables two transistors to be stacked and integrated into the size of a single transistor. This not only significantly increases transistor density but also simplifies the layout of CMOS logic circuits, enhancing design efficiency. As seen in the diagram below, n-type and p-type transistors are integrated vertically to form a CFET.

Source: imec

Nevertheless, the key challenge lies in how to vertically integrate each minuscule transistor and address heat dissipation issues under high-speed computing. Major manufacturers are still in the development phase, but the technology’s biggest advantage lies in achieving the highest component density and the smallest node width, even without nodes. With the continuous increase in demand for high-speed computing, 3D-IC technology is set to become a focal point in the industry’s development.

3D Stacking Leading the Global Semiconductor Advancement

imec has outlined a roadmap for 3D stacking, aiming to reduce pitch spacings and increase point density within unit areas. However, imec also emphasizes that the development of 3D packaging technologies does not follow a linear timeline, as depicted in the figure above, as there is no single packaging technology that can cater to all requirements.

With the rapid development of applications such as AIGC, AR/VR, 8K, 5G, and others, a significant demand for computing power is expected to persist. To overcome the bottlenecks in semiconductor process technology, countries worldwide are fully engaged in advanced packaging research, and 3D stacking undoubtedly takes the center stage as the elixir for Moore’s Law continuation.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

(Image: Samsung)

As semiconductor fabrication technologies continue to advance, the number of transistors in integrated circuits (ICs) has steadily increased. Initially, ICs contained only tens of transistors, but as technology progressed, ICs integrating hundreds of thousands of transistors enabled the realization of 3D animation. ICs with millions of transistors allowed computers to enter households, and today, ICs with hundreds of billions or even trillions of transistors enable digital technology to connect the entire world, profoundly impacting people’s lives.

Over the past 65 years, semiconductor fabrication processes have rapidly evolved, driven by Moore’s Law, gradually reshaping society. However, in recent years, semiconductor processes have approached physical limits, and the failure of Moore’s Law has been a topic of concern. In response, 3D IC stacking and heterogeneous integration technologies have emerged as promising solutions.

3D Stacking Trends

With the rapid development of applications such as AI, AR/VR, and 8K, a significant demand for computation is expected to continue, particularly driving parallel computing systems capable of handling vast amounts of data in a short time. As semiconductor processes slow down, 3D packaging has become an effective means to extend Moore’s Law and enhance IC computing performance.

3D packaging technology offers numerous advantages over traditional 2D packaging. It enables size reduction, with silicon interposer efficiency exceeding 100%, improved connectivity, reduced parasitic effects, lower power consumption, lower latency, and higher operating frequencies. These advantages, along with various benefits of 3D integration and interconnection technologies, make 3D packaging a development direction pursued by major players in the industry.

imec’s Vision for 3D Technology

In the field of 3D stacking technology, imec (imec, the Belgian Interuniversity Microelectronics Centre) defines four categories of 3D integration solutions: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC, each requiring different process solutions and 3D integration techniques. Eric Beyne, VP R&D, Director 3D System Integration Program at imec specifically notes that concerning 3D interconnection technology, the scope of 3D interconnection will extend from stack packaging below 1 millimeter (mm), such as Package-on-Package (POP), to below 100 nanometers (nm) with true 3D ICs using transistor stacking, surpassing an interconnect density of 108/mm².

imec identifies three key elements in 3D integration technology: Through-Silicon Via (TSV), die-to-die and die-to-wafer stacking and interconnection, and wafer-to-wafer bonding technology. Beyne points out that TSV miniaturization technology continues to evolve. However, regarding “interconnect gaps,” as TSVs further shrink, microbump technology may struggle to meet higher interconnection demands, making cu-cu hybrid bonding technology a focus of development.

▲The image shows imec’s 3D interconnect technology roadmap, illustrating that as packaging technology continues to advance, node sizes shrink, and density further increases in 3D packaging. (Source：ISSCC 2021)

3D-SIP

System-in-Package (SIP), a form of system-level packaging, connects multiple chips that undergo different fabrication processes and preliminary packaging using heterogeneous integration techniques, integrating them within the same packaging shell. 3D-SIP involves vertically stacking multiple SIP chips, including packaging interconnects, fan-out wafer-level packaging, and solder ball bonding.

▲The image on the left is a schematic diagram of 3D-SIP packaging, where the connection points on both sides of the PCB board link the chips that have undergone initial packaging from top to bottom. The image on the right is an actual product illustration. (Source：TrendTorce (Left)，ISSCC 2021(Right))

Currently, the connection pitch in existing solutions is approximately 400 micrometers (µm). imec’s research aims to increase the interconnectivity of such SIPs by 100 times, reducing connection pitch to 40 µm. Common applications of 3D-SIP packaging include RF FEMs, TWS Barbuds SoCs.

3D-SIC

The second category, 3D-SIC (Stacking IC), involves the stacking of individual chips on top of each other. 3D-SIC is achieved by stacking chips on an interposer or wafer, with the finished chips bonded to the top of the wafer. Chips are interconnected through TSVs and microbumps, with industry solutions achieving pitch sizes as small as 40 µm. The technology is applied to products like 3D-DRAM and logic chips, connected alongside optical I/O units on the interposer. Currently, 3D-SIC technology is widely used in High-Bandwidth Memory (HBM) manufacturing.

▲The image depicts a schematic diagram of 3D-SIC, which utilizes cu-cu hybrid bonding technology to connect the upper and lower layers of ICs. (Source:imec)

3D stacking packaging is leading the global semiconductor industry, and imec has outlined a development blueprint focused on reducing interconnection pitch and increasing contact density per unit area, positioning 3D stacking as a solution to continue Moore’s Law amid slowing semiconductor processes.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC )