Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, stated that 3D IC is a crucial method for integrating AI chip memory with logic chips.

According to a report from TechNews, regarding the development of 2.5D CoWoS advanced packaging, which integrates eight chiplets, TSMC will use the A16 advanced process to manufacture the chiplets, and integrated them with 12 HBM4, which is expected to be launched in 2027.

Reportedly, in his speech at the Semicon Taiwan 2024 “3D IC / CoWoS for AI Summit,”  He noted that the global semiconductor market is projected to become a trillion-dollar industry by 2030, with HPC and AI being the key drivers, accounting for 40% of the market, which also make AI chips crucial drivers for 3D IC packaging.

The reasons customers choose to manufacture AI chips with 3D IC platform for multi-chiplet design would be related to their lower costs and reduced design transition burdens.

Jun He explained that by converting a traditional SoC+HBM design to a chiplet and HBM architecture, the new logic chip would be the only component that needed to be designed from scratch, while other components such as I/O and SoC can use existing process technologies. This approach reduces mass production costs by up to 76%.

Although the new architecture might increase production costs by 2%, the total cost of ownership (TCO) is improved by 22% due to these efficiencies, He noted.

However, 3D IC still faces challenges, particularly in increasing production capacity. Jun He emphasized that the key to enhancing 3D IC capacity lies in the size of the chips and the complexity of the manufacturing process.

Regarding chip size, larger chips can accommodate more chiplets, improving performance. However, this also increases the complexity of the process, which can be three times more challenging. Additionally, there are risks associated with chip misalignment, breakage, and failure during extraction.

To address these risk challenges, Jun He identified three key factors: tool automation and standardization, process control and quality, and the support of the 3DFabric manufacturing platform.

For tool automation and standardization, TSMC’s differentiated capabilities with its tool suppliers are crucial. With 64 suppliers now involved, TSMC has gained the ability to lead in advanced packaging tools.

In terms of process control and quality, TSMC utilizes high-resolution PnP tools and AI-driven quality control to ensure comprehensive and robust quality management. Finally, the 3DFabric manufacturing platform integrates 1,500 types of materials within the supply chain to achieve optimization.

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(Photo credit: TSMC)

According to a report from BusinessKorea, memory giant SK hynix is deepening its collaboration with TSMC and NVIDIA, and will announce a closer partnership at the Semicon Taiwan exhibition in September.

SK hynix has been collaborating with TSMC for many years. In 2022, TSMC announced the establishment of the OIP 3DFabric Alliance at its North America Technology Symposium, incorporating partners in memory and packaging.

At that time, Kangwook Lee, Senior Vice President and PKG Development Lead at SK hynix, revealed that the company has been closely working with TSMC on previous generations and current high-bandwidth memory (HBM) technologies, supporting compatibility with the CoWoS process and HBM interconnectivity.

After joining the 3DFabric Alliance, SK hynix reportedly plans to deepen its collaboration with TSMC to develop solutions for the next generation of HBM, looking to achieve innovations in system-level products.

SK hynix President, Justin Kim, is reportedly said to be delivering a keynote speech at the International Semiconductor Exhibition in Taipei in September, marking SK hynix’s first participation in such a keynote address. Following the speech, Kim will engage in discussions with senior executives from TSMC, possibly including NVIDIA CEO Jensen Huang, to discuss collaborative plans for the next generation of HBM. This move is expected to further solidify the trilateral alliance between SK hynix, TSMC, and NVIDIA.

Notably, the collaboration among the three giants was hinted in the first half of this year. On April 25th, SK Group Chairman Chey Tae-won traveled to Silicon Valley to meet with NVIDIA CEO Jensen Huang, potentially related to these strategies.

Reportedly, SK hynix will adopt TSMC’s logic process to manufacture the base die for HBM (High Bandwidth Memory). Reports indicate that SK hynix and TSMC have agreed to collaborate on the development and production of HBM4, scheduled for mass production in 2026.

HBM stacks core chips vertically on the base die, which are interconnected. While SK hynix currently produces HBM3e using its own process for the base die, it will switch to TSMC’s advanced logic process for HBM4. The same report further suggested that SK hynix will highlight achievements at forums, including achieving more than a 20% reduction in power consumption compared to initial targets for HBM4.

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(Photo credit: SK hynix)