After TSMC released its Q3 guidance at the earnings call last week, eyeing for at least a 7.5% revenue growth, it is now said that the foundry giant has got another major boost for the following quarters. According to a report from Technews, citing Chinese media outlet ijiwei, the company is said to receive an increase in orders for Super Hot Run (SHR) from Chinese clients, and they are willing to pay up to 40% extra.

Sources cited by the reports indicated these rush orders may come from Chinese tech heavyweights, including Bitmain, Alibaba’s T-Head, and Sanechips, which are urgently stockpiling chips due to escalating tensions between the U.S. and China.

In fact, according to information from TSMC’s previous earnings conference, sales generated from orders by TSMC’s Chinese clients in the second quarter of 2024 increased from 9% of total wafer revenue in the previous quarter to 16%.

The reports stated that Chinese chip manufacturers are accelerating their pace for placing orders in response to the uncertainties arising from the upcoming U.S. presidential election and its impact on U.S.-China relations. This move is expected to provide support for TSMC’s revenue and gross margins afterwards, which may help its performance in the third quarter and the full year to exceed forecasts.

TSMC raised its projected revenue growth for 2024 to over 25% last week, thanks to the robust demand for high-end smartphones and artificial intelligence (AI) devices, which is expected to boost the use of advanced 3nm and 5nm chips.

Previous reports have indicated that TSMC is facing overwhelming demand for its 3nm technology, with major clients like Apple and NVIDIA eagerly booking for more capacity, while orders are expected to be filled through 2026. Now it seems that the demand from China has also been heating up.

Reportedly, TSMC is planning to raise its 3nm prices by over 5%, and advanced packaging prices are anticipated to increase by approximately 10% to 20% next year.

To meet this robust demand, TSMC plans to increase monthly production capacity to 130,000 wafers for its 3nm process and 160,000 to 170,000 wafers for its 4/5nm processes.

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• [News] TSMC Projects 7.5% Q3 Revenue Growth, Adjusts Full-Year CAPEX Range
• [News] Chinese Firms Stockpile Chips Amid Geopolitics; TSMC Sees Rush Orders

(Photo credit: TSMC)

As the industry is entering the Angstrom era with semiconductor giants eagerly applying EUV machines to the advanced nodes, more details about Samsung’s 2nm have surfaced. According to the latest report by TheElec, Samsung’s 2nm process will feature 30% more extreme ultraviolet (EUV) layers than the 3nm node.

The report notes that Samsung’s 3nm node has 20 EUV mask layers, while the layers of the 2nm node will be increased to late-20. As the cost of manufacturing rises with the number of EUV mask layers, whether the wafer average selling price of Samsung’s 2nm will significantly increase attracts attention.

According to the report, the South Korean semiconductor giant first implemented EUV technology in its logic process nodes with 7nm in 2018. Since then, Samsung has increased the number of EUV layers or process steps with each subsequent node, moving from 5nm to 3nm. The report also states that Samsung’s 1.4nm process, set to begin production in 2027, is expected to feature over 30 EUV layers.

Meanwhile, Samsung is also using EUV in its DRAM production. For its Gen 6 10nm DRAM, Samsung has implemented up to 7 EUV layers, compared to 5 layers used by SK Hynix, TheElec states.

In comparison, according to an earlier report by AnandTech, TSMC’s standard N3 node includes up to 25 EUV layers. TSMC employs EUV double-patterning on some of these layers to achieve greater logic and SRAM transistor density compared to its N5 node.

It is also worth noting that as EUV layers increase with each node, foundries are vying to secure more EUV machines from ASML. The Dutch lithography equipment giant is said to ship over 70 EUV machines to TSMC in 2024 and 2025 in response to the strong demand of 2nm and 3nm, according to a report by MoneyDJ.

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• [News] Samsung Officially Secures Its First 2nm Order, Making AI Chips for Preferred Networks
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)

MediaTek and Qualcomm’s new wave of 5G flagship smartphone chip competition will begin in the fourth quarter. MediaTek is launching the “Dimensity 9400” to directly compete with Qualcomm’s “Snapdragon 8 Gen 4.” According to a report from Economic Daily News, both major manufacturers are using TSMC’s 3nm process to produce their new chips, which have recently entered the production phase.

Alongside this, NVIDIA, AMD, and Apple are also actively seeking TSMC’s 3nm capacity, resulting in TSMC securing another order and seeing a surge in its advanced process business.

It is understood that the queue for TSMC’s 3nm process capacity has extended all the way to 2026. To ensure the smooth launch of the Dimensity 9400, MediaTek has already started production at TSMC to secure sufficient supply capacity. The 3nm process is currently the most advanced node technology. Previously, TSMC mentioned that its 3nm process capacity will triple this year, but it still remains in short supply.

At the beginning of this year, MediaTek CEO Rick Tsai announced that the Dimensity 9400 would be unveiled in the fourth quarter. He stated that its performance would far exceed that of the current flagship chip, the Dimensity 9300, and that it would represent another significant peak in their technology.

MediaTek’s current flagship Dimensity 9300/9300+ chips are built using TSMC’s 4nm process. Reportedly, it is expected that with the support of TSMC’s 3nm process, the performance of the Dimensity 9400 will be further enhanced, making it a powerful tool for MediaTek to capture the market.

Although Qualcomm has not yet announced the launch schedule and details of its next-generation flagship chip, the Snapdragon 8 Gen 4, the same report believed that this chip will also be produced using TSMC’s 3nm process and will be launched in the fourth quarter, with upgraded performance.

Ming-Chi Kuo, renowned Apple analyst, previously reported that the Snapdragon 8 Gen 4 will be produced using TSMC’s N3E process, and its price may be 25% to 30% higher than the current Snapdragon 8 Gen 3, with each chip priced at $220 to $240.

In the second half of the year, numerous AI products will be launched in the consumer market. Per industry sources cited in an earlier report from Commercial Times, besides Qualcomm’s Snapdragon 8 Gen 4 and MediaTek’s Dimensity 9400,  Apple’s A18 and M4 series are also said to be built using TSMC’s N3 family. Moreover, Google’s Tensor G5 may compete in the market as well.

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• [News] IC Design Companies Adopting TSMC’s 3nm Process Trigger Cost-driven Price Hikes
• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
  

(Photo credit: Qualcomm)

Google’s Tensor G4 could mark Samsung’s last mass-produced SoC, as earlier in May, Tensor G5 is reportedly adopting TSMC’s advanced 3nm process. Now here’s the latest development. According to a report by Wccftech, the chip, to be used in Google’s upcoming Pixel 10 lineup, has already reached tape-out, with mass production expected in 2025.

Google’s Tensor G5 would be its first fully self-designed smartphone SoC. Previous Tensor chips, somehow, were modifications from Samsung’s Exynos series, with Samsung being its foundry partner.

The report stated that Google’s decision to collaborate with TSMC is influenced by the Taiwanese semiconductor company’s established reliability in mass-producing wafers using its next-generation nodes.

Before Google, the foundry behemoth has already secured several major clients for its 3nm node. Both Qualcomm and Taiwanese smartphone fabless company MediaTek have reportedly adopted TSMC’s N3E node for their first 3nm chipsets. Apple’s upcoming A18 chips for iPhone 16 models, are said to be manufactured with TSMC’s N3E node as well, according to a report by Commercial Times.

On the other hand, regarding the progress of 3nm, Samsung is still struggling with the low yield rate for its latest Exynos 2500 processors. The company targets to increase the yield rate to over 60% before the product enters mass production, according to a previous report by Korean media outlet ZDNet Korea.

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• [News] Google Reportedly Shifts Orders from Samsung to TSMC for Its Upcoming Tensor G5 in the Pixel 10 Series

(Photo credit: Google)

Rumors have been circulating regarding Samsung’s 3nm yield recently. The latest market speculation on June 25^th alleged that Samsung’s foundry plant encountered a defect impacting 2,500 lots in the 3nm second-generation process, reportedly leading to a loss of 1 trillion won (USD 720 million), according to the latest report by the Chosun Daily.

On June 26^th, the semiconductor giant denied the rumors of a major defect in the production of semiconductor wafers at its foundry division in South Korea. Market speculations emerged earlier, suggesting that all the affected wafers, which equal to 2,500 lots, had to be discarded, the report noted. The volume corresponds to roughly 65,000 12-inch equivalent wafers per month.

According to the Chosun Daily, Samsung claimed that the rumor of “discarding them (the affected wafers) all” circulating in the stock market are unfounded. The current status of the products from the affected production line is still under evaluation, the report said.

Citing industry insiders familiar with the matter, the Chosun Daily noted that the reported figures might be exaggerated, pointing out that Samsung’s 3nm production capacity is less than 60,000 wafers per month. Furthermore, there are numerous inspection processes in place throughout the production line, indicating that such a large-scale defect may be improbable.

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• [News] Samsung’s 3nm Yield Reportedly Below 20%, Struggling for Mass Production

(Photo credit: Samsung)