Benefited from frequent orders from its top three clients, Apple, Intel, and AMD, strong momentum has reportedly been driven for TSMC’s 3-nanometer orders, as per a report from Economic Daily News. Anticipated to see sequential growth throughout the year, these orders are expected to remain robust until the end of the year, positioning TSMC as a leader in the semiconductor industry’s recovery.

TSMC has a longstanding policy of not commenting on customer order dynamics. However, it is cited in the report that in the fourth quarter of last year, 3-nanometer orders accounted for approximately 15% of its revenue. With the adoption of 3-nanometer production by major clients this year, revenue from 3-nanometer orders is expected to surpass 20%, becoming the second-largest revenue contributor, following only the 5-nanometer process.

Looking at the orders placed by the top three clients for the 3-nanometer process, Apple is set to introduce the A18 series processor in its iPhone 16 lineup this year. Additionally, the latest self-developed M4 chip for laptops will also be produced by TSMC using the 3-nanometer process, starting in the second quarter.

On the Intel side, the Lunar Lake central processor, graphics processor, and high-speed IO chip are all confirmed to begin mass production at TSMC in the second quarter. This marks Intel’s first instance of outsourcing its entire mainstream consumer platform chip series to TSMC, making it a significant new source of orders for TSMC’s 3-nanometer process this year.

AMD, on the other hand, is poised to unveil its new Zen 5 architecture platform under the code name “Nirvana” this year, expected to significantly enhance AI applications. Following its customary practice, AMD will utilize TSMC’s wafer foundry services, with production set to commence on the 3-nanometer process and an expected launch in the latter half of the year.

TSMC, reportedly, is expanding its production capacity for the 3nm family and advanced packaging this year to meet the large orders from major clients such as Apple, NVIDIA, and AMD in the coming years.

As per TrendForce’s data, the 3nm process alone contributed 6% to TSMC’s Q3 revenue, with advanced processes (≤7nm) accounting for nearly 60% of its total revenue.

Read more

• [News] Apple Reportedly Places Large Orders for TSMC’s 3nm While Simultaneously Securing Significant Advanced Packaging Capacity
• [News] TSMC Reportedly Attracts Influx of 3nm Customers, Predicts Production Capacity Utilization to Surge to 80% by Year-End

(Photo credit: TSMC)

Shortly after the release of the MacBook Air with the built-in M3 chip, a report from MacRumors has cited the report that Apple is already working on the development of the next-generation M4 chip, expected to be launched next year.

As per Mark Gurman revealed in a Q&A with Bloomberg, Apple has officially commenced the development of the M4 chip, which is expected to debut alongside the next-generation MacBook Pro. Reportedly, there’s a possibility that the M4 chip may adopt TSMC’s 2nm process. TSMC’s related process is scheduled to undergo first tool-in this year and commence mass production next year.

As per MacRumors’ report, following the introduction of the first in-house developed M1 chip by Apple in November 2020, Apple has consistently pursued chip upgrades. In June 2022, Apple unveiled the M2 chip, followed by the release of the M3 chip at the end of October last year.

With approximately a year and a half gap between each generation of chips, it is speculated by MacRumors that Apple will unveil the M4 chip in the first half of next year. Some sources cited in the report also believe that Apple’s accumulated experience in chip development in recent years may enable them to shorten the development timeline, potentially leading to the announcement of the M4 chip by the end of this year.

However, compared to the 3nm process used in the M3 chip, the 3nm process of the M4 chip could be an upgraded version, with improvements in both computational capability and energy efficiency.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures and is anticipated to commence mass production in 2025, so the M4 chip may still adopt the 3nm process.

As for TSMC’s 2-nanometer process, a previous report from wccftech has indicated that Apple is expected to adopt the 2nm process for chip production in the iPhone 17 by 2025.

Read more

• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] Apple Reportedly Places Large Orders for TSMC’s 3nm While Simultaneously Securing Significant Advanced Packaging Capacity

(Photo credit: Apple)

The annual AI event, NVIDIA GTC (GPU Technology Conference), is set to take place on March 17th, as H200 and the next-generation B100 will reportedly be announced ahead of schedule to seize the market. According to Commercial Times’ report citing sources, H200 and the upcoming B100 will adopt TSMC’s 4-nanometer and 3-nanometer processes respectively. H200 is expected to be launched in the second quarter, while it’s rumored that orders for the B100 adopting Chiplet architecture have already been placed for production.

Sources cited by the report also indicate that NVIDIA’s orders are robust, pushing TSMC’s 3 and 4-nanometer production capacity to near full utilization, making the first quarter, traditionally a slow season, unexpectedly busy.

Regarding the matter of NVIDIA’s next-generation chip orders overwhelming TSMC’s advanced processes, TSMC stated that details regarding production capacity remain consistent with the previous earnings call and will not be elaborated further.

Still, Commercial Times further cited industry sources, revealing that TSMC, in response to anticipated capacity constraints by 2023, is accelerating its efforts. Particularly focusing on advanced packaging like CoWoS, they’ve not only relocated equipment from the Longtan facility but also swiftly activated the AP6 plant in Zhunan.

Another industry sources reportedly indicate that the planned construction of the Tongluo
facility, initially slated for the second half of this year, is now scheduled to commence in the second quarter. The aim is to ramp up 3D Fabric capacity to produce 110,000 12-inch wafers per month by the first half of 2027.

Meanwhile, TSMC’s advanced processes remain fully utilized, with capacity utilization exceeding 90% in February, driven by sustained AI demand.

NVIDIA, on the other hand, recently emphasized that computational-intensive tasks like Generative AI and large language models require multiple GPUs. From customer purchase to model deployment, it takes several quarters. Thus, this year’s inference applications stem from GPU purchases made last year. As model parameters grow, GPU demand is expected to expand.

In addition to increasing GPU quantities, NVIDIA’s GPU efficiency is poised for a significant boost this year. The Blackwell series, notably the B100, is hailed as NVIDIA’s next-generation GPU powerhouse by the market.

Not only is it the first to adopt TSMC’s 3-nanometer process, but it’s also the pioneer in Chiplet and CoWoS-L packaging among NVIDIA products. This tackles high power consumption and cooling issues, with projected single-card efficiency and transistor density expected to surpass AMD’s MI300 series set to debut in the first quarter.

Read more

• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC
• [News] NVIDIA CEO Jensen Huang Meets with TSMC Executives in Taiwan, Addressing the Significant AI Chip Shortage

(Photo credit: Kioxia)

Apple’s product line is rumored to set for a significant upgrade. According to a report from Economic Daily News, the next-generation M4 and A18 processors, slated for iPads, MacBooks, and iPhones, are expected to increase the number of built-in AI computing cores, leading to a substantial growth in orders to TSMC. Consequently, TSMC’s production volume for its enhanced 3-nanometer process this year is forecasted to surge by over 50% compared to last year.

As per a report cited by the Economic Daily News, Apple, recognizing the significant AI trend, is not only significantly enhancing the AI computing power of the M3 and A17 processors this year, but also increasing the number and efficiency of AI computing cores in the next-generation M4 and A18 processors. The AI application adoption rate across all product lines is expected to greatly increase.

Apple is strengthening the AI computing performance of its terminal devices and significantly increasing the computational power of its in-house processors, resulting in a simultaneous substantial increase in orders to TSMC.

The report further cited sources indicating that Apple’s orders for TSMC’s enhanced 3nm process this year are rumored to increase by over 50% compared to last year, solidifying its position as TSMC’s largest customer.

In addition to increasing orders for TSMC’s wafer production, reportedly, Apple has also secured a significant amount of advanced packaging capacity from TSMC. Industry sources cited by the Economic Daily News has indicated that Apple primarily places orders with TSMC for advanced packaging processes such as InFO and CoWoS, which are 2.5D advanced packaging technologies.

This year, there is a possibility that Apple will push its advanced packaging requirements to the highest price and difficulty level, such as the 3D structure SoIC advanced packaging.

TSMC, reportedly, is expanding its production capacity for the 3nm family and advanced packaging this year to meet the large orders from major clients such as Apple, NVIDIA, and AMD in the coming years.

As per TrendForce’s data, the 3nm process alone contributed 6% to TSMC’s Q3 revenue, with advanced processes (≤7nm) accounting for nearly 60% of its total revenue.

TSMC had previously announced during its earnings call that its capital budget for this year is expected to fall between USD 28 billion to USD 32 billion, with 70% to 80% allocated for advanced processes, 10% to 20% for specialty processes, and the remaining 10% for advanced packaging, testing, and mask production.

Read more

• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC
• [News] TSMC’s Primary Client for 2nm Chips Expected to be Apple, Set to Debut with iPhone 17 Lineup Next Year

(Photo credit: TSMC)

Samsung’s flagship mobile processor, the Exynos 2400, produced using the 4LPP+ process technology, currently boasts a yield rate of approximately 60%, as per sources cited by TechNews. While this figure falls short of competitors, notably TSMC’s N4P process technology with yields surpassing 70%, it represents a significant improvement from Samsung’s own 25% yield rate over a year ago.

Samsung’s Exynos 2400 flagship mobile processor is the company’s first to utilize Fan-Out Wafer-Level Packaging (FOWLP). Samsung claims that FOWLP technology enhances heat resistance by 23% and boosts multicore performance by 8%. Consequently, the Exynos 2400 mobile processor delivers commendable performance in the latest 3DMark Wild Life benchmark tests.

In fact, Samsung previously announced plans to commence mass production of the SF3 chip in the second half of 2024, followed by the introduction of its 2-nanometer process technology between 2025 and 2026.

Industry sources cited in the report also indicate that Samsung’s foundry business has begun trial production for its second-generation 3-nanometer process technology, SF3. Furthermore, the company aims to increase its yield rate to over 60% within the next six months.

It is noteworthy that Samsung’s 3nm technology is highly aggressive compared to TSMC’s approach, which will transition to GAA transistors with its 2nm process. Samsung’s first-generation 3nm process already incorporates GAA transistor technology, specifically the MBCFET (Multi-Bridge Channel Field-Effect Transistor), known as SF3E, or 3GAE technology.

As per WeChat account ic211ic cited sources in the report, Samsung’s 3nm GAA technology utilizes wider nanosheets compared to the narrow nanowire GAA technology, offering higher performance and energy efficiency. With the 3nm GAA technology, Samsung can adjust the channel width of nanosheet transistors to optimize power consumption and performance, meeting diverse customer requirements.

Additionally, the flexibility of GAA design is highly advantageous for Design-Technology Co-Optimization (DTCO), contributing to achieving better Power, Performance, and Area (PPA) advantages.

In comparison to Samsung’s 5nm process, the first-generation 3nm process reduces power consumption by 45%, enhances performance by 23%, and decreases chip area by 16%. The upcoming second-generation 3nm process is expected to further reduce power consumption by 50%, boost performance by 30%, and reduce chip area by 35%.

(Photo credit: Samsung)