According to a report from wccftech,  previous claims about Xiaomi abandoning the development of its smartphone processor due to high costs were incorrect. Instead, Xiaomi is expected to release its custom solution in the first half of 2025, with its performance rumored to be equivalent to Qualcomm’s Snapdragon 8 Gen 1, which was released two years ago. The chip is said to be manufactured with TSMC’s 4nm process.

The chip, as per wccftech citing sources, will be produced using TSMC’s N4P process,  which is a generation behind the Qualcomm’s Snapdragon 8 Gen 4 and MediaTek’s Dimensity 9400. However, as the shipment volume might be not as high, it is reasonable that Xiaomi might not need to opt for the most advanced manufacturing process.

Although TSMC has already introduced its 3nm process and is advancing towards 2nm, its 4nm N4P process is still competitive, as both the Snapdragon 8 Gen 3 and Dimensity 9300 are produced with N4P.

The sources also indicate that the performance of Xiaomi’s in-house chip is similar to that of Snapdragon 8 Gen 1’s, while the 5G modem chip will be supplied by another Chinese company, Unisoc. Xiaomi’s move towards developing its own smartphone chips is expected to its reduce reliance on Qualcomm and MediaTek.

Shanghai-based fabless chip firm Unisoc, is specialized in areas including 2G/3G/4G/5G, Wi-Fi, Bluetooth, TV FM, satellite communications and other related technologies, according to its website.

Per a previous report from wccftech, Qualcomm executives had hinted that the Snapdragon 8 Gen 4 will be more expensive than the Snapdragon 8 Gen 3, and they may also charge partners for the 5G modem chip. By developing its own chips, Xiaomi can gain valuable experience and gradually reduce its dependence on Qualcomm.

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• [News] MediaTek and Xiaomi Opened a Joint Lab, the First Product with Stellar Performance Unveiled
• [News] China’s Xiaomi and Unisoc Claim Domestic 4nm Mobile Processors Coming Soon

(Photo credit: Xiaomi)

On August 13, Google officially released the Pixel 9 series of smartphones, featuring Google’s latest self-developed Tensor G4 processor and advanced AI function supported by Gemini AI.

Google Pixel 9 series includes three full-screen smartphones: Pixel 9, Pixel 9 Pro, and Pixel 9 Pro XL, as well as a foldable smartphone, the Pixel 9 Pro Fold.

Both Pixel 9 and Pixel 9 Pro are equipped with 6.3-inch screens, with the Pixel 9 Pro using a better LTPO screen; Pixel 9 Pro XL is fitted with a 6.8-inch screen; Pixel 9 Pro Fold’s internal screen size increased from 7.6 inches to 8 inches, and the external display screen size from 5.8 inches to 6.3 inches.

The base memory capacity of the new phones is up to 12GB, with the two Pro models and the Pixel 9 Pro Fold offering 16GB of memory.

It is learned that the Tensor G4 adopted in Google’s new phones is based on Samsung’s 4nm process (4LPP+), boasting a 3.1GHz Arm Cortex-X4 super core, three 2.6GHz Arm Cortex-A720 large cores, and four 1.92GHz Arm Cortex-A520 small cores.

Moreover, Tensor G4 is equipped with the new Samsung Exynos Modem 5400 baseband chip (Outside the processor), supporting 4G/5G, WiFi-7, Bluetooth 5.x, and satellite connectivity. The memory used is LPDDR5X, and media decoding supports formats such as H.264, H.265, VP9, and AV1.

Read more

• [News] Google’s Tensor G5 Reportedly Manufactured with TSMC’s 3nm and InFO-POP Packaging
• [News] Google Reportedly Shifts Orders from Samsung to TSMC for Its Upcoming Tensor G5 in the Pixel 10 Series

(Photo credit: Google)

Amid the wave of AI applications, the demand for high-performance memory continues to mushroom, with DRAM, represented by HBM, gaining significant traction. Meanwhile, to further meet market demand, memory manufacturers are  poised to embrace a new round of DRAM technological “revolution.”

• 4F Square DRAM being Developed Smoothly

According to a report from Korean media outlet Chosun Biz, Samsung Electronics Vice President Changsik Yoo recently announced that Samsung’s next-generation DRAM technology is progressing well. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also proceeding smoothly, with the initial sample of 4F Square DRAM set to be developed by 2025.

Industry sources cited by WeChat account DRAMeXchange indicate that the early DRAM cell structure was 8F Square, while currently commercialized DRAM mainly uses 6F Square. Compared to these two technologies, 4F Square employs a vertical channel transistor (VCT) structure, which can reduce the chip surface area by 30%.

As the cell area decreases, DRAM density and performance increase. Therefore, driven by applications like AI, 4F Square technology is gradually sought after by major storage manufacturers.

Previously, Samsung stated that many companies are working to transition their technology to 4F Square VCT DRAM, although some challenges need to be overcome, including the development of new materials like oxide channel materials and ferroelectrics.

Industry sources believe that the initial sample of Samsung’s 4F Square DRAM in 2025 might be for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will come out between 2027 and 2028.

Furthermore, earlier media reports mentioned that Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is a next-generation packaging technology referring to vertically stack chips to increase cell density and thus improve performance, which will also exert an influence on the development of HBM4 and 3D DRAM.

• HBM4 on the Horizon

In the era of AI, HBM, particularly HBM3e, has thrived in the memory market, prompting fierce competition among the three major DRAM manufacturers. A new race is now underway, primarily focusing on the next-generation HBM4 technology.

In April of this year, SK Hynix announced a partnership with TSMC to jointly develop HBM4. It is reported that the two companies will first work on performance improvements for the base die fitted at the bottom layer within the HBM package. To focus on the development of next-generation HBM4 technology, Samsung has established a new “HBM Development Team.”

In July, Choi Jang-seok, head of the New Business Planning Group in Samsung Electronics’ memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, expected to go into production next year. Recently, Samsung reportedly plans to use a 4nm advanced process to produce HBM4 logic die. Micron, on the other hand, plans to introduce HBM4 between 2025 and 2027 and transition to HBM4E by 2028.

Aside from manufacturing processes, DRAM manufacturers are actively exploring hybrid bonding technology for future HBM products. Compared to existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed, better matching the high bandwidth requirements of AI computing.

In April of this year, Korean media outlet The Elec reported that Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, with the memory sample functioning normally. This 16-layer stacked hybrid bonding technology will be used to produce HBM4 at scale in the future. SK Hynix plans to adopt hybrid bonding in its HBM production by 2026. Micron is also developing HBM4 and is considering related technologies, including hybrid bonding, which are all under research at present.

• The Development of 3D DRAM Picks up Steam

3D DRAM (Three-dimensional dynamic random-access memory) represents a new DRAM technology with a novel memory cell structure. Unlike traditional DRAM, which places memory cells horizontally, 3D DRAM vertically stacks memory cells, greatly increasing storage capacity per unit area and improving efficiency. This makes it a key development for the next generation of DRAM.

In the memory market, 3D NAND Flash has already achieved commercial application, while 3D DRAM technology is still under research and development. However, as AI, big data, and other applications enjoy burgeoning growth, the demand for high-capacity, high-performance memory will surge, and 3D DRAM is expected to become a mainstream product in the memory market.

HBM technology has paved the way for the 3D evolution of DRAM, enabling DRAM to transition from traditional 2D to 3D. However, current HBM cannot be considered as true 3D DRAM technology. Samsung’s 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in 3D DRAM.

Samsung plans to achieve the commercialization of 3D DRAM by 2030. In 2024, Samsung showcased two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, then upgraded to stacked DRAM by stacking multiple VCTs together to continuously improve DRAM capacity and performance.

Samsung states that stacked DRAM can fully utilize the Z-axis space, accommodating more memory cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung noted that it, along with other companies, successfully manufactured 16-layer 3D DRAM, but emphasized that it is not ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and BSPDN (Backside Power Delivery Network) technology is also considered.

Regarding Micron, industry sources cited by DRAMeXchange reveal that Micron has filed for a 3D DRAM patent application different from Samsung’s, aiming to alter the shape of transistors and capacitors without placing cells.

BusinessKorea reported in June that SK Hynix achieved a manufacturing yield of 56.1% for its 5-layer stacked 3D DRAM. This means that out of around 1000 3D DRAMs produced on a single test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM demonstrated characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix disclosed specific numbers and features of its 3D DRAM development.

Besides, American company NEO Semiconductor is also engaging in the development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world’s first 3D DRAM prototype: 3D X-DRAM. This technology resembles 3D NAND Flash, namely increasing memory capacity by stacking layers, offering high yield, low cost, and remarkably high density.

NEO Semiconductor plans to launch the first generation of 3D X-DRAM in 2025, featuring a 230-layer stack and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.

Read more

• [News] Korean Semiconductor Exports Hit a New High, with Memory Shipment up by 88.7%
• [News] Korean Advanced Packaging Industry’s Rise Delayed by TSMC and ASE Expansion

(Photo credit: SK Hynix)

As per a report from Korea Economic Daily citing unnamed sources on July 15th, Samsung Electronics is preparing to mass-produce the logic die for HBM4 using its advanced 4nm process.

The logic die, situated at the bottom of the chip stack, is a core component of HBM. Memory manufacturers are already capable of producing logic dies for existing products like HBM3e. However, regarding HBM4, the sixth-generation model, with its custom features demanded by customers, requires additional wafer processing steps.

Reportedly, Samsung’s 4nm process, which boasts is said boasting a yield rate exceeding 70%, is one of their flagship technologies. This advanced process is also used in producing the Exynos 2400 processor for their flagship AI smartphone, the Galaxy S24.

An industry source cited by the report further stated that the 4nm process is much costlier than the 7nm and 8nm but significantly better in terms of chip performance and power consumption. Reportedly, Samsung, which manufactures HBM3e with the 10nm process, is looking to take the throne in the HBM sector by applying the 4nm process.

On the other hand, SK Hynix announced its collaboration with TSMC in April 2024. In a statement released on April 19th, SK Hynix stated that the two semiconductor giants will collaborate on developing the 6th generation HBM4 chips, with production scheduled for 2026.

The same report from the Korean Economic Daily also addressed that, Samsung has reportedly deployed employees from its System LSI division to the newly established HBM research team. In response to Samsung’s actions, SK Hynix and TSMC have decided to add the 5nm process in addition to the originally planned 12nm process for producing the logic die of HBM4.

Read more

• [News] Samsung Develops Custom HBM with Tech Giants, with Commercialization Expected in HBM4
• [News] Samsung Establishes New HBM Team to Advance HBM3, HBM3e and HBM4 Development

(Photo credit: Samsung)

According to the industry sources cited in a report from Economic Daily News, TSMC is gearing up to start production of NVIDIA’s latest Blackwell platform architecture graphics processors (GPU) on the 4nm process. In response to the strong customer demand, NVIDIA has reportedly increased its orders to TSMC by 25%.

This surge not only underscores the unprecedented boom in the AI market but also provides substantial momentum for TSMC’s performance in the second half of the year, setting the stage for an optimistic annual outlook adjustment, the report notes.

TSMC is set to hold an earnings conference call on July 18, in which it is expected to release the financial results of the second quarter as well as the guidance for the third quarter.

As TSMC will reportedly commence the production of NVIDIA’s Blackwell platform architecture GPU, which may be regarded as one of the most powerful AI chips, it is anticipated to be a focal point of discussion at TSMC’s upcoming earnings call.

Packed with 208 billion transistors, NVIDIA’s Blackwell-architecture GPUs are manufactured using a custom-built 4NP TSMC process with two-reticle limit GPU dies connected by 10 TB/second chip-to-chip link into a single, unified GPU.

The report further cited sources, revealing that international giants such as Amazon, Dell, Google, Meta, and Microsoft will adopt the NVIDIA Blackwell architecture GPU for AI servers. As demand exceeds expectations,NVIDIA is prompted to increase its orders with TSMC by approximately 25%.

As NVIDIA ramps up production of its Blackwell architecture GPUs, shipments of terminal server cabinets, including the GB200 NVL72 and GB200 NVL36 models, have seen a simultaneous significant increase. Initially expected to ship a combined total of 40,000 units, this figure has surged to 60,000 units, marking a 50% increase. Among them, the GB200 NVL36 accounts for the majority with 50,000 units.

The report estimates suggest that the average selling price of the GB200 NVL36 server cabinet is USD 1.8 million, while the GB200 NVL72 server cabinet commands an even higher price of USD 3 million. The GB200 NVL36 features 36 GB200 super chips, 18 Grace CPUs, and 36 enhanced B200 GPUs, whereas the GB200 NVL72 boasts 72 GB200 super chips, 36 Grace CPUs, and 72 B200 GPUs, which all contribute to TSMC’s momentum.

TSMC former Chairman Mark Liu, before handing over the reins in June, had already predicted that the demand for AI applications looks more optimistic compared to a year ago. Current Chairman C.C. Wei has also indicated that AI applications are just beginning, and he is optimistic like everyone else.

Read more

• [News] End of an Era under Mark Liu’s Leadership, TSMC Discusses Future Development Plans
• [News] TSMC’s 4nm Process Powers NVIDIA’s Blackwell Architecture GPU, AI Performance Surpasses Previous Generations by Multiples

(Photo credit: TSMC)