In early September, rumors have it that TSMC’s first US fab in Arizona began producing engineering wafers using the 4nm process in April, with yields reportedly comparable to those manufactured in its Southern Taiwan Science Park facility. Now here’s the latest update: the fab has started trial production for Apple’s A16 chip, according to a report by MoneyDJ.

The report notes that the mobile processors are manufactured with TSMC’s 5nm, or the so-called N4P node, which is the same as the node used in Taiwan to manufacture A16. The N4P node is actually a member of the 5nm family, as it is regarded as an enhanced version of 5nm, the report explains.

It is worth noting that Apple’s A16 SoC, though launched two years ago with iPhone 14 Pro, is considered as one of the most advanced mobile chips for the company, as the chip is also be seen in iPhone 15 and iPhone 15 Plus models. MoneyDJ indicates that the move marks a milestone that instead of beginning with some less critical chips, Apple and TSMC intend to aim high from the start.

According to the report, Apple’s A16 is currently being trial-produced at TSMC Arizona’s “Fab 21” Phase 1 facility, with a small production volume. However, once the second stage of the Phase 1 fab is completed, the output will significantly increase.

TSMC plans to build three plants in Arizona, each with cleanroom spaces twice the size of typical logic fabs in the industry. The first fab is expected to begin mass production in the first half of 2025.

TSMC’s second fab in Arizona will use 2nm process technology to meet strong AI-related demand, with production expected to begin in 2028. The third fab will employ 2nm or even more advanced process.

However, the situation for Samsung’s investment in the U.S. would be a different story. A previous report from Korean media outlet Business Korea noted that persistent issues with its 2nm yield rate have led Samsung to decide to withdraw personnel from its Taylor, Texas plant, signaling another setback for its advanced wafer foundry business.

As for Intel, which proactively pursues the support of the U.S. government, it is holding steadfast on its investments in the country despite recent announcements to spin-off its foundry business and delaying the projects in Germany and Poland for two years.

Intel plans to invest USD 100 billion over the next five years in new fabs and expansions across Arizona, New Mexico, Ohio, and Oregon, creating 10,000 manufacturing jobs and 20,000 construction jobs.

Read more

• [News] Showing Positive Progress, TSMC’s Arizona Fab Reportedly Reaches Production Yields on Par with Taiwan
• [News] TSMC Receives USD 6.6 Billion for Chipmaking from the US Government, Commits to Constructing Third Fab

(Photo credit: Apple)

Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, stated that 3D IC is a crucial method for integrating AI chip memory with logic chips.

According to a report from TechNews, regarding the development of 2.5D CoWoS advanced packaging, which integrates eight chiplets, TSMC will use the A16 advanced process to manufacture the chiplets, and integrated them with 12 HBM4, which is expected to be launched in 2027.

Reportedly, in his speech at the Semicon Taiwan 2024 “3D IC / CoWoS for AI Summit,”  He noted that the global semiconductor market is projected to become a trillion-dollar industry by 2030, with HPC and AI being the key drivers, accounting for 40% of the market, which also make AI chips crucial drivers for 3D IC packaging.

The reasons customers choose to manufacture AI chips with 3D IC platform for multi-chiplet design would be related to their lower costs and reduced design transition burdens.

Jun He explained that by converting a traditional SoC+HBM design to a chiplet and HBM architecture, the new logic chip would be the only component that needed to be designed from scratch, while other components such as I/O and SoC can use existing process technologies. This approach reduces mass production costs by up to 76%.

Although the new architecture might increase production costs by 2%, the total cost of ownership (TCO) is improved by 22% due to these efficiencies, He noted.

However, 3D IC still faces challenges, particularly in increasing production capacity. Jun He emphasized that the key to enhancing 3D IC capacity lies in the size of the chips and the complexity of the manufacturing process.

Regarding chip size, larger chips can accommodate more chiplets, improving performance. However, this also increases the complexity of the process, which can be three times more challenging. Additionally, there are risks associated with chip misalignment, breakage, and failure during extraction.

To address these risk challenges, Jun He identified three key factors: tool automation and standardization, process control and quality, and the support of the 3DFabric manufacturing platform.

For tool automation and standardization, TSMC’s differentiated capabilities with its tool suppliers are crucial. With 64 suppliers now involved, TSMC has gained the ability to lead in advanced packaging tools.

In terms of process control and quality, TSMC utilizes high-resolution PnP tools and AI-driven quality control to ensure comprehensive and robust quality management. Finally, the 3DFabric manufacturing platform integrates 1,500 types of materials within the supply chain to achieve optimization.

Read more

• [News] TSMC Plans Rapid CoWoS Expansion Through 2026 in Response to Client Demand
• [News] TSMC Rumored to Build New CoWoS Plant in Southern Taiwan

(Photo credit: TSMC)

TSMC’s angstrom-level A16 process is creating a buzz even before mass production. According to a report from the Economic Daily News, not only has major client Apple already booked the capacity for TSMC’s A16, OpenAI has also joined in to secure TSMC’s A16 capacity due to its long-term need for self-developed AI chips.

Regarding this matter, TSMC stated on August 30 that the company does not comment on market rumors or on business dealings with individual customers.

Despite that TSMC’s A16 process is scheduled to enter mass production in 2026, the report has hinted that the first batch of customers has already surfaced.

In addition to Apple, which has been in continuous collaboration with TSMC, the most notable new customer of TSMC’s A16 is said to be OpenAI, the developer of ChatGPT, which is actively investing in the design and development of its own ASIC chips.

Industry sources cited by the same report reveal that OpenAI had initially been in active discussions with TSMC about establishing a dedicated fab. However, after assessing the potential benefits, the plan to build a dedicated facility was shelved.

Strategically, OpenAI is now partnering with U.S. companies like Broadcom and Marvell to develop its own ASIC chips, and potentially emerging as one of Broadcom’s top four customers.

Since both IC design giants are long-term clients of TSMC, the ASIC chips they are helping OpenAI develop are expected to be produced using TSMC’s 3nm process family and the subsequent A16 process, according to the chip design roadmap.

It is worth noting that OpenAI not only holds a critical position in the development of AI applications beyond Apple’s ecosystem but also contributes to the advancement of AI applications in Apple devices.

In June of this year, Apple unveiled its personalized intelligent system, Apple Intelligence, which has integrated ChatGPT. This strategic move has led observers to believe that OpenAI plays a key role in Apple’s AI development.

As OpenAI continues to invest in the design and development of its own ASIC chips, it is reportedly expected to maintain its influence in the AI computing field.

TSMC unveiled its angstrom-class A16 advanced process during the company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026.

Per TSMC, Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Read more

• [Insights] OpenAI CEO’s Ambition to Build Semiconductor Plant Grows Stronger
• [News] Battle of the Titans in the Angstrom Era – TSMC’s A16 Competes with Intel’s 14A and Samsung’s SF1.4

TSMC is set to offer a new round of its CyberShuttle prototyping service in September. According to sources cited in a report from Commercial Times, it’s revealed that, as per usual practice, there are two opportunities each year, in March and September, for customers to submit their projects. It is indicated that the highlight this time is expected to be the 2nm process, providing leading companies with an opportunity to gain an edge.

TSMC’s 2nm technology is progressing smoothly, with the new Hsinchu Baoshan plant on track for mass production next year. Previously, there were rumors indicating that Apple is considering adopting 2nm chips in 2025, with the iPhone 17 series potentially being among the first devices to use them.

Reportedly, both TSMC’s N2P and A16 technologies are expected to enter mass production in the second half of 2026, offering improvements in power efficiency and chip density.

ASIC companies are eagerly participating in CyberShuttle this time, even though customer intentions for the first 2nm tape-out are still unconfirmed. However, this technology will likely maintain TSMC’s leadership in advanced processes, securing its future technological advantage.

CyberShuttle, also known as MPW (Multi-Project Wafer), refers to the process of placing chips from different customers onto the same test wafer. This approach not only allows for the shared cost of photomasks but also enables rapid chip prototyping and verification, enhancing customers’ cost efficiency and operational effectiveness.

Based on TSMC’s official information, the CyberShuttle prototyping service significantly reduces NRE costs by covering the widest technology range (from 0.5um to 7nm) and the most frequent launch schedule (up to 10 shuttles per month), all through the Foundry segment’s most convenient on-line registration system.)

TSMC’s CyberShuttle prototyping service also validate the sub-circuit functionality and process compatibility of IP, standard cell libraries and I/Os, reducing prototype costs by up to 90%. TSMC states that their current CyberShuttle service covers the broadest range of technologies and can offer up to 10 shuttles per month.

TSMC’s 2nm technology is expected to make its debut in September, offering opportunities for test chips.

Per the report from Commercial Times, IC design companies have pointed out that, unlike the familiar FinFET (Fin Field-Effect Transistor) structure, the industry is transitioning to the Gate-All-Around FET (GAAFET) structure, making it crucial for the market to quickly adapt.

This also allows IC design companies to provide related products to end customers, demonstrating their 2nm design capabilities.

ASIC companies have also revealed that, based on CyberShuttle data, the number of advanced process projects below 7nm is relatively small, with mature processes still dominating.

This suggests that future competition will likely focus on a few leading companies. Those who miss the first wave of 2nm technology may fall behind their competitors by up to six months, making securing a spot on the Shuttle even more critical.

Read more

• [News] TSMC Reportedly to Raise 3nm & 5nm Prices Soon, Looking to Maintain Long-Term Profit Margins 
• [News] Apple Not Adopting TSMC 2nm for iPhone 17? A19 Pro Chip Rumored to Use N3P Process

(Photo credit: TSMC)

If you happen to be a technology enthusiast, June would certainly be a month to watch. NVIDIA CEO Jensen Huang, joined by AMD CEO Lisa Su, visited Taiwan to announce their product roadmaps in COMPUTEX 2024. NVIDIA unveiled its new generation Rubin architecture, indicating that the R series products are expected to go into mass production in the fourth quarter of 2025.

On the other hand, AMD introduced its Ryzen AI 300 Series processors with the world’s most powerful Neural Processing Unit (NPU) for next-gen AI PCs, featuring a new Zen 5 CPU, as well as its latest AI chips, MI325X and MI350.

Interestingly enough, on 4 June, the world’s largest semiconductor foundry, TSMC, held its shareholders’ meeting in Hsinchu, Taiwan. When asked about the company’s relationships with NVIDIA and AMD, President C.C. Wei has reaffirmed TSMC’s strong relationships with the two tech giants, saying that the company will prosper with its clients.

What will be the highlights for TSMC’s progress in advanced logic process, and what are some of the most advanced products introduced in COMPUTEX made with TSMC’s advanced nodes? Please proceed to find out more. For now, TSMC’s 3nm seems to be the most popular node.

N3 Family

TSMC’s N3E (the more cost-effective second generation of the 3nm process) entered mass production in the fourth quarter of 2023. On the other hand, N3P (a more advanced version) is scheduled to enter mass production in the second half of 2024. Its yield performance is close to that of N3E, while customer product designs have already been tape-out.

TSMC states that due to N3P’s superior performance, better power consumption and area (PPA) characteristics, most 3nm products will eventually adopt the node. In the future, the industry may expect to see more high-end products manufactured with 3nm.

Regarding capacity, driven by the strong demand from HPC and mobile phone, TSMC has tripled its 3nm capacity in 2024 compared to that of 2023. However, as it is still not enough, the world’s largest semiconductor foundry has been striving to meet customer demand.

Intel’s Lunar Lake/ Arrow Lake

At COMPUTEX 2024, Intel CEO Pat Gelsinger introduced Lunar Lake, its latest AI PC chip, and thank its friend “TSMC” for their full support.

Starting Q3 2024 in time for the holiday season, Lunar Lake will power more than 80 new laptop designs across more than 20 original equipment manufacturers.

In a previous report by Wccftech, Gelsinger stated that Intel has collaborated with TSMC to power up its next-gen CPUs, adopting N3B, the first-generation 3nm process, for Lunar Lake and Arrow Lake.

NVIDIA’s Rubin

On the other hand, NVIDIA’s Rubin GPU architecture is now official: the Rubin GPU will feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, noted by Jensen Huang, CEO of NVIDIA.

Per a report from Wccftech, NVIDIA’s Rubin GPU is expected to utilize TSMC’s CoWoS-L packaging technology, along with its N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.

Regarding NVIDIA’s previous GPUs, according to Commercial Times’ report, H200 and B100 reportedly are said to adopt TSMC’s 4-nanometer and 3-nanometer processes, respectively.

AMD’s MI 325X/ MI350

On 3 June, AMD CEO Lisa Su stated that the company’s relationship with TSMC is “very strong,” even as rumors have been circulating about a potential partnership with Samsung, TSMC’s main competitor.

AMD unveiled the company’s latest AI chip, MI325X, at the opening of COMPUTEX Taipei. Su emphasized that the MI325X boasts 30% faster computing speed compared to NVIDIA’s H200.

Furthermore, she also announced that AMD will release MI350 in 2025, which will be manufactured with TSMC’s 3nm process, while MI400 is expected to follow, launched in 2026.

When asked if AMD intended to procure chips manufactured using Samsung’s 3-nanometer (3nm) gate-all-around (GAA) process, Su reiterated AMD’s commitment to utilizing “the most advanced technology,” saying that AMD is certainly going to use 3 nm, 2 nm, and beyond. She also confirmed that there are several 3nm products currently being developed in collaboration with TSMC.

In addition to TSMC’s collaboration with clients on 3nm, this article also curates TSMC’s progresses on its 2nm node and other advanced processes. More information below:

N2 Family

The N2 process utilizes nanosheet transistors, thus would be able to offer superior energy efficiency. Currently, TSMC’s 2nm technology is progressing smoothly, with nanosheet conversion performance reaching the target of 90%, indicating that the yield exceeds 80%. Mass production is expected in 2025.

In the future, TSMC states that more members of the N2 family will emerge, including applications like N2P and N2X.

Read more

• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year
• [News] Samsung Reportedly Doing Its Utmost to Win 3nm GPU Orders from NVIDIA

(Photo credit: TSMC)