On June 18th, Belgium’s microelectronics research center IMEC showcased the first CMOS CFET device featuring stacked bottom and top source/drain contacts at the 2024 IEEE VLSI Technology and Circuits Symposium (2024 VLSI). Although the results were achieved using front-side lithography techniques for both contacts, imec also demonstrated the feasibility of transferring the bottom contacts to the back side of the wafer, which potentially increases the survival rate of top devices from 11% to 79%.

IMEC explained that their logic technology roadmap envisions the introduction of Complementary Field-Effect Transistor (CFET) technology into device architectures at the A7 node. Paired with advanced wiring technologies, CFET is expected to reduce the standard cell height from 5T to 4T or even lower without sacrificing performance. Among the different approaches to integrating vertically stacked nMOS and pMOS structures, monolithic integration is considered the least disruptive compared to existing nanosheet process flows.

At VLSI Symposium 2024, IMEC demonstrated for the first time a functional monolithic CMOS CFET device with both top and bottom contacts. The device features a gate length of 18nm, a gate pitch of 60nm, and a vertical distance of 50nm between the n-type and p-type. The process flow IMEC’s proposed includes two CFET-specific modules: Middle Dielectric Isolation (MDI) and stacked bottom and top contacts.

MDI is a module pioneered by IMEC to isolate the top and bottom gates and to differentiate threshold voltage settings between n-type and p-type devices. Based on modifications to the “active” multilayer Si/SiGe stack in CFET, MDI module allows for the co-integration of internal spacers—a feature unique to nanosheets that isolates the gate from the source/drain.

“We obtained the best results in terms of process control with an MDI-first approach, i.e., before source/drain recess – the step where nanosheets and MDI are ‘cleaved’ to gain access to the channel sidewalls and start source/drain epi. An innovative source/drain recess etch with ‘in-situ capping’ enables MDI-first by protecting the gate hardmask/gate spacer during the source/drain recess.” stated Naoto Horiguchi, IMEC’s CMOS device technology director, as per a report from IMEC.

The second critical module is the formation of stacked source/drain bottom and top contacts, vertically separated by dielectric isolation. Key steps involve bottom contact metal filling and etching, followed by dielectric filling and etching—all completed within the confined space of the MDI stack.

Naoto Horiguchi noted that developing bottom contacts from the front side encountered many challenges, which potentially impacts bottom contact resistance and limits the process window for top devices. At VLSI 2024, IMEC indicated that despite additional processes like wafer bonding and thinning, this design is proved feasible, making the backside bottom contact structure an attractive option for the industry. Currently, research is underway to determine the optimal contact wiring method.

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(Photo credit: IMEC)