ACM Research, Inc., a provider of wafer processing solutions for semiconductor and advanced wafer-level packaging applications in China, announced on September 3rd the release of its Ultra C bev-p panel bevel etching tool for fan-out panel-level packaging (FOPLP) applications.

This new tool is designed for bevel etching and cleaning in copper-related processes, offering dual-side bevel etching for both the front and back of panels within a single system, further boosting process efficiency and enhances product reliability.

Moreover, a day after the announcement, the company further revealed that it had received purchase orders for four wafer-level packaging tools, including two from a U.S.-based customer and two from a U.S.-based research and development (R&D) center.

Dr. David Wang, ACM’s president and chief executive officer, believes that FOPLP will grow in importance as it addresses the evolving needs of modern electronic applications, offering benefits in integration density, cost efficiency, and design flexibility.

Reportedly, the new Ultra C bev-p tool is designed to deliver advanced performance, utilizing ACM’s expertise in wet processing. It is one of the first tools to incorporate double-sided bevel etching for horizontal panel applications.

Together with the Ultra ECP ap-p for electrochemical plating and the Ultra C vac-p flux cleaning tools, the Ultra C bev-p is expected to support the FOPLP market by enabling advanced packaging on large panels with high-precision features.

ACM emphasizes that the Ultra C bev-p tool is a critical enabler for FOPLP processes, employing a wet etching technique tailored for bevel etching and copper residue removal.

This process plays a vital role in preventing electrical shorts, reducing contamination risks, and preserving the integrity of subsequent processing steps, ensuring long-term device reliability. The tool’s effectiveness is driven by ACM’s patented technology, designed to tackle the specific challenges of square panel substrates.

Different from traditional round wafers, ACM’s design is said to ensure precise bevel removal process that stays confined to the bevel region, even on warped panels. This is essential for maintaining the integrity of the etching process while ensuring the high performance and reliability needed for advanced semiconductor technologies.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

Read more

• [News] ACM Research Steps into FOPLP Advanced Packaging Field
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)

Amid the advancement of emerging applications such as Artificial Intelligence (AI), High-Performance Computing (HPC), data center, and autonomous vehicle, fan-out panel-level packaging (FOPLP) technology has successfully garnered industry attention due to its advantages in significantly improving computing power, reducing latency, and increasing bandwidth. As a result, more manufacturers are entering this field.

Recently, semiconductor equipment manufacturer ACM Research Shanghai introduced the Ultra ECP ap-p panel-level electroplating equipment for FOPLP.

Prior to this, ACM has launched the Ultra C vac-p negative pressure cleaning equipment designed for fan-out panel-level packaging applications, signaling that ACM has successfully entered the high-growth FOPLP market.

It is worth mentioning that since the second quarter of this year, chip manufacturers like AMD have actively approached TSMC and professional OSAT (Outsourced Semiconductor Assembly and Test) companies to promote chip packaging using FOPLP technology, further increasing industry focus on FOPLP.

In fact, advanced packaging has an increasing demand for low-latency, high-bandwidth, and cost-effective semiconductor chips, and FOPLP offers high bandwidth and high-density chip interconnects, making it a technology with higher potential.

FOPLP is a process performed on larger square substrates, allowing multiple chips, passive components, and interconnects to be integrated into a single package on a panel, offering greater flexibility, scalability, and cost effectiveness.

By redistributing chips on larger rectangular panels, FOPLP largely reduces the costs of packaging large GPU and high-density, high-bandwidth memory (HBM).

It is reported that the utilization rate of traditional silicon wafers is less than 85%, while that of panels exceeds 95%. The effective area of a 600×600 mm panel is 5.7 times that of a 300 mm traditional silicon wafer, with overall panel cost expected to decrease by 66%.

The increase in area utilization leads to higher capacity, greater flexibility in AI chip design, and significant cost reduction.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages, facing both opportunities and challenges. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

Read more

• [News] Innolux Targets to Begin FOPLP Mass Production by Year-End
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)