The surge in AIGC and new technologies such IoT, AI, 5G, AR/VR are driving a huge demand for computational power of high-end chips. This has been even outpacing the performance increase offered by the long-standing Moore’s Law, ushering in a “post-Moore” era where revolutions in advanced chip design are crucial.

Over recent years, chiplet design has seemingly become the mainstream approach for upgrading high-end chips. The concept is to allow more transistors on a single chip, effectively increasing the production yield of high-end chips while reducing overall costs.

By the large, major IC players have all jumped on board. Even Apple has joined the game by releasing their M1 Ultra SoC using the chiplet concept, which doubles computational performance by integrating two M1 Max units in a single chip.

The CPU sector is definitely a clear demonstration of this trend:

• AMD took the leap with chiplet design in their 2nd-gen EPYC CPUs, doubling the computing cores from 32 to 64 within two years, while slashing costs by up to half. The company has extended this approach to their 4th-gen EPYC CPUs and even pioneered the GPU Navi 31, the first of its kind to use chiplets.
• Intel started incorporating chiplets into their Lakefield series SoC in 2020. Looking ahead, their upcoming CPUs like the Meteor Lake set for 2023, and Arrow Lake and Lunar Lake scheduled for 2024, will all use chiplet design.

Transition from Bumping to Hybrid Bonding

Our analysis in “Chiplet Design: A Real Game-Changer for Substrates” laid out the comprehensive impact of the evolution of chiplet technology on substrates. In fact, chiplets have already caused a significant disruption to the most advanced semiconductor packaging technologies, necessitating the transition towards advanced 2.5D and 3D packaging technologies.

The bottleneck of advanced packaging lies in the chiplets’ interconnections, with bump and microbump still being the key technology for linking chips and forming I/O joints. These connection densities are hard to enhance, thus limiting the overall chip’s transmission speed. In addition, the more chiplets being stacked, the bigger the chip volume gets. The challenge is how to limit the chip size within a specific range, considering the current technical constraints.

Therefore, copper-to-copper hybrid bonding, also known as DBI (Direct Bond Interconnect), has been emerging as the key technology route that overcomes major hurdles in chiplet integration from the bottom-up.

Unlike bumping technology, hybrid bonding significantly shrinks the I/O joint space. The future transmission demand requires the I/O joint space between chiplets to be less than 10µm. While bumping is limited to around 20µm, hybrid bonding can take this down to an impressive 1µm or even less. This also means more I/O joints can be fitted in the same chip size – even reaching up to millions on a mere 1cm2 chip.

On top of this, hybrid bonding only adds an extra 1-2µm of thickness, compared to the 10-30µm of microbump, thereby helping reduce the thickness of stacked chips.

To put it simply, hybrid bonding can boost transmission efficiency, minimize energy usage with higher density of copper joints, manage chip volume, and even cut down on material costs.

The Race for Advanced Packaging Is Kicking Off

Moving forward, hybrid bonding is set to become the key technology supporting the continuous development of chiplet design and 3D packaging. This has been exemplified by TSMC’s front-end So IC packaging technology which is based on hybrid bonding. This puts AMD, a key customer of TSMC, in a favorable position to get ahead.

From AMD’s roadmap of 3D V-Cache technology, they have stacked SRAM on top of CCX (CPU Complex), and gradually integrated it into Milan-X series, the EPYC server CPUs, and Ryzen series, the consumer-grade CPUs, over the past two years. This has significantly improved performance and power consumption as a whole.

Not to be outdone, this year Intel also launched their Foveros Direct packaging technology, which is also based on hybrid bonding route. Assuming everything proceeds smoothly, we can anticipate the release of CPUs utilizing Foveros Direct technology by 2024.

As we look at the current products, AMD’s hybrid bonding apparently focuses on stacking SRAM and computing units at the moment. However, as CPU leaders deepen their understanding of this technology, the application field is expected to further expand. In other words, the future of hybrid bonding solutions stacking multiple computation units is just around the corner.

According to TrendForce research, driven by strong demand for 5G mobile phones, base stations, automobiles, and HPCs, the global output value of packaging and testing (including foundry and IDM) reached US$82.139 billion in 2021, or 25.83% YoY. This upward momentum is forecast to continue in 2022, taking output value to US$101.185 billion in 2022, or 23.19% YoY. From the perspective of regional distribution, China’s IC packaging and testing output value in 2021 was approximately US$39.443 billion, increasing 31.7% compared with US$29.941 billion in 2020, becoming the world’s fastest-growing major market in terms of packaging and testing output value.

Shanghai pandemic lengthens overall lead time, hinders China’s packaging and testing growth in 2Q22

In 2Q22, Shanghai was locked down due to the COVID-19 pandemic. Although wafer fabs and packaging and testing plants were still operating normally, the pandemic hindered logistics and the materials required for packaging could not be effectively shipped from Shanghai, affecting transportation efficiency and logistics costs to a certain degree. Overall, China’s packaging and testing industry was not significantly affected by the pandemic in 1Q22 but, in 2Q22, the industry will bear the brunt of the COVID-19 situation, with packaging and testing companies experiencing prolonged overall lead times and sluggish revenue growth.

NEVs and HPCs to become new growth drivers, fabs and packaging and testing companies accelerate deployment

The growth rate of smartphones, a core driving force behind IC packaging and testing output value, is slowing down. Since smartphone shipments peaked at 14.575 million units in 2017, volume has not surpassed this number in the ensuing years. Even though the upgrade from 4G to 5G brought about a wave of replacements, the overall smartphone market has reached maturity, with slowing growth or even negative growth, so its demand on wafer manufacturing and packaging and testing is likewise slowing down.

Aside from mobile phones, growth in HPC and new energy vehicles (NEV) is becoming a new revenue engine. At present, the world’s major automobile production countries are accelerating the penetration rate of NEVs, and packaging and testing companies are also accelerating their investment in the automotive and HPC sectors. From the perspective of fabs, TSMC’s HPC revenue accounted for 41% of total packaging and testing revenue in 1Q22, surpassing mobile phones for the first time and becoming the largest source of the company’s packaging and testing revenue.

（Image credit: Unsplash）

As the COVID-19 pandemic wreaked havoc on the global electronics supply chain, the packaging and testing operations of mid-range and high-end chips were subsequently confronted with prolonged lead times. This can primarily be attributed to the fact that IC substrate suppliers were unable to raise output or expand their production capacities in the short run in order to meet the skyrocketing volume of client orders. Hence, products that are packaged using BGA (Ball Grid Array), Flip Chip, or SiP technologies, all of which require the use of IC substrates, had their lead times lengthened. Certain IC design companies are therefore considering the feasibility of packaging technologies that do not require substrates.

Regarding the trend of advanced packaging development, technologies such as 2.5D/3D IC, SiP, and FOPLP (Fan-out Panel Level Packaging) remain the current mainstream R&D targets. Given the ongoing shortage of semiconductor components, including IC substrates, FOPLP, in particular, has garnered the most attention among the aforementioned three packaging technologies as it can be operated without substrates. At present, most OSAT companies and other chipmakers have successively invested in FOPLP-related technological and manufacturing development in order to capitalize on potential new commercial opportunities.

Despite FOPLP’s advantage of packaging chips across large areas, technological development remains problematic

Regarding the history of FOPLP development as well as the technology’s evolution going forward, its earliest roots can be traced to existing packaging applications including Flip Chip and BGA. As end-products continued to experience performance upgrades, leading to the number of I/O pins being insufficient for meeting the increase in performance demand, new types of wafer-level packaging technologies such as Fan-in and Fan-out subsequently emerged to fulfill the packaging demands of mid-range chips, high-end chips, and other emergent applications.

Although Fan-in and Fan-out packaging technologies are able to effectively raise the number of I/O pins, they also result in a substantial increase in manufacturing costs compared to previous-generation technologies such as Flip Chip and BGA. For both 8-inch wafers and 12-inch wafers, packaging costs have only been on a very slight downtrend. That is why the packaging industry has placed a top priority on simultaneously lowering production costs while raising the number of chips packaged at once. Hence, FOPLP technology has emerged in response to this demand for large-area packaging technology.

Regarding the actual implementation of FOPLP, a potential solution may be found in wafer-level packaging RDL (Redistribution Layer) designs, such as chip first or chip last. It should be noted that chip first FOWLP or chip last FOWLP processes do in fact serve as feasible concepts for FOPLP development. However, the FOPLP process involves stacking massive amounts of packaging materials and chips together, and their combined weight may lead to such issues as panel warpage. In addition, it remains difficult to maintain a consistent uniformity and yield rate during the FOPLP process, meaning further collaborations and optimizations on the parts of OSAT companies and semiconductor equipment suppliers are necessary for FOPLP to succeed going forward.

（Image credit: Unsplash）

The rise of such products as automotive, industrial, telecom, and networking chips in recent years has resulted in continued advancements in packaging and testing technologies, and the market revenue of these technologies has seen a corresponding rise as well. Demand for advanced packaging has been relatively strong thanks to high demand for 5G smartphones, consumer electronics, and high-performance processors.

In particular, the mainstream development of advanced packaging and testing is currently concentrated on three major fields: HPC chip packaging（2.5D/3D）, FOPLP（fan out panel level packaging）, and SiP（system in package）. Some of the other factors driving forward the technological development of advanced packaging also include improvements in end product functions, advancements in transistor gate sizes, reduction in advanced packaging L/S, and migration of chip interconnect technology from micro-bumping to hybrid bond.

According to TrendForce’s investigations, the advanced packaging market last year reached a revenue of US$31.037 billion in 2020（which was a 13% increase YoY）and accounted for 45.8% of the total packaging market. At the moment, most packaging and testing companies have successively entered the advanced packaging market, with Flip Chip applications accounting for the majority of applications across smartphone AP, WiFi chips, entry-level processors, and high-end PMICs. Flip Chip applications make up more than 80% of the total advanced packaging revenue.

In spite of continued growth, advanced packaging will unlikely overtake traditional packaging in terms of market share within 5-10 years

In spite of the multitude of companies that are eager to enter the advanced packaging industry, not all of them possess the technological competence to progress in R&D, thus making acquisition the fastest path to advanced packaging success. With regards to technological competence, foundries and IDMs are the likeliest candidates to enter the industry, as they already possess ample experience in chip development.

At the moment, TSMC, Intel, and Samsung are the most well-equipped to do so, respectively. With regards to outsourced operations, Taiwanese companies such as ASE, SPIL, and PTI lead the industry in terms of packaging technologies, while U.S.-based Amkor is able to compete for neck-and-neck with ASE. Although these aforementioned companies are not specialists in chip fabrication, they have an extremely strong grasp of the downstream assembly ecosystem, hence their superiority in advanced packaging.

On the other hand, thanks to China’s Big Fund, the trinity of Chinese packaging and testing operators（JCET, TFME, and Hua Tian）were able to acquire major global players, including STATS ChipPac, AMD-SUZ, and Malaysia-based Unisem, respectively, during the 2014-2019 period.

Hence, not only have the Chinese trio been able to raise their market shares and rankings in the global packaging and testing market, but they have also been able to acquire certain competencies in advanced packaging technologies.

The current market would seem to suggest that advanced packaging has been gradually cannibalizing the market share of traditional packaging. However, as applications including home appliances and automotive electronics still require traditional packaging, TrendForce believes that only after 5-10 years will advanced packaging overtake traditional packaging in terms of market share.

（Cover image source: TSMC）