According to a report from UDN, China’s largest semiconductor packaging and testing company, JCET, has completed the planning and verification work for the first phase of the “JCET Microelectronics Wafer-level Microsystems Integration High-end Manufacturing Project.”

The project will soon be completed and put into production. Once operational, it will have an annual production capacity of 6 billion high-end advanced packaging chips, providing one-stop services from collaborative packaging design to chip production for 5G, artificial intelligence, and other applications.

As per WeChat account DRAMeXchange citing sources, the project is a major industrial initiative in Jiangsu Province, China, with a total investment of CNY 10 billion. Upon completion of the first phase, the project will have an annual production capacity of 6 billion high-end advanced packaging chips.

The project will focus on leading-edge high-performance packaging technologies, such as 2.5D/3D high-density wafer-level packaging. JCET Microelectronics commenced construction of its new plant in the eastern part of Jiangyin City on July 29, 2022, with the project expected to be completed and put into production between June and July 2024.

At the groundbreaking ceremony in 2022, JCET CEO Zheng Li stated that this project will represent the highest production technology level and largest single-investment smart manufacturing project in China’s integrated circuit packaging and testing and chip manufacturing industry. Thus, it will support end applications such as 5G, artificial intelligence, the Internet of Things, and automotive electronics, covering key strategic customers worldwide.

This project, per Li, will further enhance JCET’s global market competitiveness in the chip manufacturing sector, aiming to achieve a higher industrial position in the global integrated circuit industry.

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(Photo credit: JCET Group)

As TSMC stands at the core of the global semiconductor industry, NVIDIA founder Jensen Huang stirred up an AI frenzy when he visited Taiwan in June. According to a report from Commercial Times, during his visit, he met with TSMC founder Morris Chang and then-President C.C. Wei, and personally visited TSMC’s headquarters.

According to a report by Mirror Media on July 23rd, sources revealed that Huang requested TSMC to set up a dedicated CoWoS production line for NVIDIA at an external facility. However, this request was met with skepticism from TSMC’s senior management, resulting in a tense situation.

Notably, TSMC Chairman C.C. Wei recently pointed out that despite strong AI demand, the company has yet to achieve a supply-demand balance and continues to increase production capacity. Many customers are eager for advanced process capacity, and TSMC is striving to balance pricing and capacity. Wei also revealed that the profit margins for advanced packaging CoWoS are being adjusted to align more closely with the company’s average profit levels.

C.C. Wei emphasized TSMC’s commitment to meeting customer demands with three “Whatever” statements. Regarding timelines, he revealed that supply will remain tight through 2025, with hopes for improvement by 2026.

Sources cited by the report further estimates that current utilization rates for 5nm and 3nm processes are at full capacity. To address demand, production for 3nm is set to increase gradually from 100,000 wafers per month to approximately 125,000 wafers per month by the second half of the year.

The 2nm process is expected to start mass production in the fourth quarter of 2025, with a target monthly output of 30,000 wafers. With future expansion at the Kaohsiung plant, the combined monthly capacity of the Hsinchu Science Park and Kaohsiung facilities is projected to reach 120,000 to 130,000 wafers.

Despite escalating geopolitical risks, Wei stated that there will be no changes to TSMC’s expansion strategy, with projects in Arizona, Japan’s Kumamoto, and future European facilities proceeding as planned.

Currently, TSMC’s investment in its U.S. facilities has reached USD 65 billion. The Arizona site is expected to have three plants, with the first two set to start production in 2025 and 2028, focusing on 4/3nm and 3/2nm nodes, respectively.

TSMC’s advanced packaging plans in Taiwan include facilities in Hsinchu Science Park, Miaoli Zhunan, Taichung Central Taiwan Science Park, Tainan Southern Taiwan Science Park (taking over Longtan InFO), and Taoyuan Longtan (significantly expanding CoWoS). Construction is also scheduled to begin in 2024 at Miaoli Tongluo and Chiayi Science Park.

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(Photo credit: TSMC)

TSMC continues to showcase its drive in the advanced packaging market. According to a report from MoneyDJ, TSMC has forecasted that CoWoS will remain in high demand through 2025, with potential for capacity to double in two consecutive years. TSMC is also entering the FOPLP (Fan-Out Panel-Level Packaging) space, a technology that OSATs and panel manufacturers have been developing for years, with a goal to launch it in three years.

TSMC’s stronghold on advanced packaging technologies has raised market concerns that OSATs may see their opportunities diminished as TSMC consolidates its market position.

During its earnings call, TSMC introduced “Foundry 2.0,” a new definition for the semiconductor manufacturing industry. This expanded definition now includes not only foundry services but also packaging, testing, photomask production, and other integrated component manufacturing, excluding memory production. TSMC further stated that this new definition will better reflect the company’s growing market opportunities and that the company will focus solely on cutting-edge back-end technologies.

Under this new definition, TSMC estimates the Foundry 2.0 industry will be nearly USD 250 billion in 2023, up from the previous estimate of USD 115 billion. With this new scope, the industry is expected to grow by 10% annually in 2024. Additionally, TSMC’s market share in Foundry 2.0 (logic semiconductor manufacturing) for 2023 is revised to 28%, with expectations for continued growth in 2024.

The sources cited by the report has pointed out that, observing TSMC’s process advancements, the 3nm process began mass production in 2022, with the 2nm process set for 2025, indicating a lengthening of the development cycle to three years.

Regarding the aforementioned nodes, advanced packaging may help enhance performance, reduce costs, and has the advantage of binding high-end products from top-tier clients. Additionally, the investment required for advanced packaging is significantly smaller compared to frontend technologies, making it a crucial area of focus.

The report continues to note that TSMC currently retains the majority of major CoWoS orders and collaborates with OSATs in the WoS segment. However, TSMC has reportedly yet finalized its CoW segment outsourcing orders.

Meanwhile, AMD and NVIDIA have reportedly turned to Amkor and ASE’s subsidiary, Siliconware, for CoWoS-related products, focusing on cost-sensitive high-performance products. Amkor is expected to supply about 70,000 to 80,000 units annually this year, while Siliconware can provide about 50,000 to 60,000 units.

Additionally, OSATs have been confined to mature IC FOPLP technologies for the past 7-8 years, whereas TSMC has announced it will launch its own FOPLP technology in three years.

TSMC’s planned FOPLP is a rectangular CoWoS-L concept, offering advantages in low unit cost and large-size packaging. However, it faces physical limitations such as issues in coating, spinning, and warping. TSMC, backed by a substantial equipment and materials supply chain, is well-positioned to address these challenges.

As for opportunities for other OSATs, the advanced packaging market is actually vast and can be broadly categorized into flip-chip, fan-out, fan-in, 2.5D/3D, and embedded die packaging.

These technologies can be integrated, and OSATs are not limited to TSMC’s top-tier Info, CoWoS, or SoIC technologies. OSATs can offer more cost-effective advanced packaging solutions compared to fabs, providing competitive alternatives in terms of cost and performance.

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(Photo credit: TSMC)

In the Q2 earnings call today (July 18th), TSMC Chairman and CEO C.C. Wei introduced the concept of “Foundry 2.0,” redefining the foundry industry to further include sectors like packaging, testing, mask making, and others, the latest report by Technews noted.

C.C. Wei pointed out that under this new definition, TSMC’s foundry market share was 28% in 2023, and the foundry industry is expected to grow by 10% in 2024, while TSMC’s share will increase further. According to data from TrendForce, under the original definition of foundry, TSMC’s market share was 61.2%.

On the other hand, the semiconductor giant projects the entire semiconductor market, excluding memory, to grow by 10% in 2024.

TSMC’s CFO and spokesperson Wendell Huang explained that the reason for TSMC to propose “Foundry 2.0” is due to the involvement of IDM manufacturers in the foundry market, which has blurred the boundaries of the traditional foundry industry.

Moreover, C.C. Wei highlighted the strong demand for TSMC’s 3nm and 5nm processes. Thanks to the strong demand from AI and smartphones for advanced nodes, Wei believes that 2024 will be a strong year for TSMC. Meanwhile, the company also expects this year’s financial forecast and revenue to increase by 24-26% (mid-20%).

TSMC’s 3nm process accounted for 15% of wafer sales revenue in the second quarter of 2024, while 5nm and 7nm accounted for 35% and 17%, respectively. Overall, revenue from advanced processes (7nm and below) reached 67% of total wafer sales revenue for the quarter.

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(Photo credit: TSMC)

With the surge in new applications like AI, advanced packaging remains a hot topic, particularly with FOPLP (Fan-Out Panel Level Packaging) technology gaining renewed attention. According to sources cited by a report from MoneyDJ, leading semiconductor foundry TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

TSMC introduced the FOWLP (Fan-Out Wafer Level Packaging) technology named InFO (Integrated Fan-Out) in 2016, first used in the iPhone 7’s A10 processor. Subsequently, assembly and testing facilities actively promoted FOPLP solutions, looking to attract customers with lower production costs, yet faced ongoing technical challenges. Therefore, current terminal applications remain within mature processes, such as PMIC (Power Management IC) products.

However, per the sources cited by the same report, TSMC’s move to transition advanced packaging technology from wafer level to panel level is more than just talk—it’s becoming a reality. It is reported that TSMC is planning to use rectangular substrates measuring 515mm by 510mm, with a dedicated team already conducting research and planning to establish a mini line.

The source further mentioned that, TSMC’s development of FOPLP can be seen as a rectangular version of InFO, offering advantages such as lower unit costs and larger package sizes.

This advancement could further integrate other technologies on TSMC’s 3D fabric platform, paving the way for 2.5D/3D advanced packaging solutions to serve high-end product applications. This approach could be regarded similar to a rectangular CoWoS, currently targeted at the AI GPU sector with NVIDIA as a customer. If progress continues smoothly, these developments could potentially debut between 2026 and 2027.

On the AMD front, it is understood that their initial partners for FOPLP are ASE Technology and PowerTech Technologies, with potential applications in PC or gaming console chips. Reportedly, it’s suggested that previous packaging methods for PCs and gaming consoles primarily used FC-BGA, but upcoming new products may potentially upgrade to CoWoS level.

Sources cited by the report note that in the early stages of FOPLP, players like PowerTech Technologies, Innolux, and ASE Technology faced challenges and intermittent demand. To allocate resources effectively, equipment suppliers have been conservative in their investments in related fields, focusing mainly on adjusting specifications to meet customer demands. With TSMC now officially joining, equipment suppliers are shifting to a more proactive stance in preparation for upcoming developments.

In summary, the development of the FOPLP ecosystem hinges largely on TSMC’s role. TSMC is expected to maintain leadership in the high-end segment, while packaging and testing firms will cater to the mid-to-high-end markets. Semiconductor experts believe that in the realm of high-speed computing, CoWoS will remain mainstream for the next 3 to 5 years, with advanced 3D packaging like SoIC gaining prominence in high-end applications, solidifying TSMC’s position as a key player.

For packaging and testing companies, the key lies in product upgrades that offer cost-effectiveness. The success of FOPLP as the next generation of advanced packaging hinges on how chip manufacturers position their products, address yield issues related to warpage, and ensure overall performance and pricing that justify customer investment.

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(Photo credit: TSMC)