As semiconductor fabrication technologies continue to advance, the number of transistors in integrated circuits (ICs) has steadily increased. Initially, ICs contained only tens of transistors, but as technology progressed, ICs integrating hundreds of thousands of transistors enabled the realization of 3D animation. ICs with millions of transistors allowed computers to enter households, and today, ICs with hundreds of billions or even trillions of transistors enable digital technology to connect the entire world, profoundly impacting people’s lives.

Over the past 65 years, semiconductor fabrication processes have rapidly evolved, driven by Moore’s Law, gradually reshaping society. However, in recent years, semiconductor processes have approached physical limits, and the failure of Moore’s Law has been a topic of concern. In response, 3D IC stacking and heterogeneous integration technologies have emerged as promising solutions.

3D Stacking Trends

With the rapid development of applications such as AI, AR/VR, and 8K, a significant demand for computation is expected to continue, particularly driving parallel computing systems capable of handling vast amounts of data in a short time. As semiconductor processes slow down, 3D packaging has become an effective means to extend Moore’s Law and enhance IC computing performance.

3D packaging technology offers numerous advantages over traditional 2D packaging. It enables size reduction, with silicon interposer efficiency exceeding 100%, improved connectivity, reduced parasitic effects, lower power consumption, lower latency, and higher operating frequencies. These advantages, along with various benefits of 3D integration and interconnection technologies, make 3D packaging a development direction pursued by major players in the industry.

imec’s Vision for 3D Technology

In the field of 3D stacking technology, imec (imec, the Belgian Interuniversity Microelectronics Centre) defines four categories of 3D integration solutions: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC, each requiring different process solutions and 3D integration techniques. Eric Beyne, VP R&D, Director 3D System Integration Program at imec specifically notes that concerning 3D interconnection technology, the scope of 3D interconnection will extend from stack packaging below 1 millimeter (mm), such as Package-on-Package (POP), to below 100 nanometers (nm) with true 3D ICs using transistor stacking, surpassing an interconnect density of 108/mm².

imec identifies three key elements in 3D integration technology: Through-Silicon Via (TSV), die-to-die and die-to-wafer stacking and interconnection, and wafer-to-wafer bonding technology. Beyne points out that TSV miniaturization technology continues to evolve. However, regarding “interconnect gaps,” as TSVs further shrink, microbump technology may struggle to meet higher interconnection demands, making cu-cu hybrid bonding technology a focus of development.

▲The image shows imec’s 3D interconnect technology roadmap, illustrating that as packaging technology continues to advance, node sizes shrink, and density further increases in 3D packaging. (Source：ISSCC 2021)

3D-SIP

System-in-Package (SIP), a form of system-level packaging, connects multiple chips that undergo different fabrication processes and preliminary packaging using heterogeneous integration techniques, integrating them within the same packaging shell. 3D-SIP involves vertically stacking multiple SIP chips, including packaging interconnects, fan-out wafer-level packaging, and solder ball bonding.

▲The image on the left is a schematic diagram of 3D-SIP packaging, where the connection points on both sides of the PCB board link the chips that have undergone initial packaging from top to bottom. The image on the right is an actual product illustration. (Source：TrendTorce (Left)，ISSCC 2021(Right))

Currently, the connection pitch in existing solutions is approximately 400 micrometers (µm). imec’s research aims to increase the interconnectivity of such SIPs by 100 times, reducing connection pitch to 40 µm. Common applications of 3D-SIP packaging include RF FEMs, TWS Barbuds SoCs.

3D-SIC

The second category, 3D-SIC (Stacking IC), involves the stacking of individual chips on top of each other. 3D-SIC is achieved by stacking chips on an interposer or wafer, with the finished chips bonded to the top of the wafer. Chips are interconnected through TSVs and microbumps, with industry solutions achieving pitch sizes as small as 40 µm. The technology is applied to products like 3D-DRAM and logic chips, connected alongside optical I/O units on the interposer. Currently, 3D-SIC technology is widely used in High-Bandwidth Memory (HBM) manufacturing.

▲The image depicts a schematic diagram of 3D-SIC, which utilizes cu-cu hybrid bonding technology to connect the upper and lower layers of ICs. (Source:imec)

3D stacking packaging is leading the global semiconductor industry, and imec has outlined a development blueprint focused on reducing interconnection pitch and increasing contact density per unit area, positioning 3D stacking as a solution to continue Moore’s Law amid slowing semiconductor processes.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC )

According to a report by Taiwan’s Economic Daily, TSMC is set to hold its Q3 earnings conference on October 19th. The market is eagerly anticipating insights from the company’s top executives on six key areas: the latest semiconductor market outlook, Q3 financial forecasts, the status of 3-nanometer chip orders, progress in advanced packaging expansion, capital expenditure updates, and the latest developments in the AI market.

During the conference, TSMC will also unveil its financial results for the previous quarter. Analysts are expecting TSMC’s Q3 consolidated revenue, when measured in USD, to grow by nearly 10%, with a chance of gross margin exceeding the company’s estimated median of 52.5%. This suggests that Q3 profits are likely to surpass those of Q2.

TSMC has already announced its combined revenue for July and August, which totaled NT$366.3 billion. Based on TSMC’s financial forecasts, Q3 consolidated revenue is expected to reach between $16.7 billion and $17.5 billion USD. Using an exchange rate of 30.8 NT dollars per USD, this translates to an expected consolidated revenue in NT dollars ranging from NT$514.4 billion to NT$539 billion.

In the first half of the year, TSMC’s capital expenditure was $9.94 billion in Q1 and $8.17 billion in Q2, totaling $18.11 billion. Securities analysts previously estimated that TSMC’s annual capital expenditure for this year could range from $32 billion to $36 billion USD, with the possibility of a decrease next year.

Some industry experts believe that as advanced manufacturing processes have advanced to 2 nanometers, the customer base for the latest processes has started to decrease. Looking at the 3-nanometer process that is already in mass production, only Apple is currently leading the adoption, while others like NVIDIA, Qualcomm, and MediaTek are expected to transition to the 3-nanometer process next year. As a result, TSMC is shifting its focus to expanding production in the more cost-effective advanced packaging sector, which is one of the key reasons for the decrease in TSMC’s capital expenditure.

Furthermore, TSMC is currently estimating that it will be the first to introduce an enhanced version of the 3-nanometer process next year, with expectations to transition to the 2-nanometer process by 2025, using a new Gate-All-Around (GAA) transistor architecture to replace the FinFET transistor architecture used for nearly a decade. This represents a significant step into a new generation of semiconductor technology. Additionally, capacity for advanced packaging is expected to double next year.

(Photo credit: TSMC)

According to a report by Taiwan’s Economic Daily, TSMC is aggressively expanding its advanced packaging capacity. Recently, they placed an additional 30% order for equipment with manufacturers, leading to a doubling of order volumes for companies in the interposer supply chain, such as UMC and ASE Group. Moreover, there are rumors of price increases on the horizon.

TSMC, responding to the robust production demands from major clients like NVIDIA, AMD, and Amazon, has not only expanded its CoWoS capacity as originally planned but has also added another 30% in new equipment. This move implies that once TSMC’s new advanced packaging capacity comes online next year, it will represent at least a doubling of the current production capacity.

Given the substantial demand for TSMC’s advanced packaging orders, coupled with the necessity of interposer in CoWoS for stacking logic computing ICs and high-bandwidth memory, there is an expectation of significant growth in interposer orders, likely exceeding a twofold increase compared to this year. Notably, semiconductor giants like UMC and ASE Group have already secured significant orders from TSMC for interposer layers and are currently in the mass production and delivery stages.

It is understood that UMC, after venturing into the advanced packaging market in recent years, has introduced packaging solutions applicable to IoT, automotive chips, and more, spanning from wafer bumping and wire bonding packaging to advanced 2.5D, 3DIC, and wafer-level fan-out packaging solutions. The most notable among them is the 2.5D silicon interposer layer solution, which, through collaboration with UMC and other specialized packaging facilities, has proven pivotal in securing major orders in the interposer layer market, particularly from NVIDIA.

Industry sources suggest that UMC has increased prices for super hot run interposer layer orders and initiated capacity expansion plans to meet customer demands, while ASE Group is also contemplating adjustments to its advanced packaging quotations.

(Photo credit: UMC)

According to Taiwan’s Business Next, as Moore’s Law gradually reaches its limits, semiconductor manufacturers are transitioning from 2D to 3D chip stacking and packaging to increase transistor counts for improved performance. The final step, “packaging,” has become crucial. In line with this trend, Intel has announced the industry’s first glass-based substrate for advanced packaging, breaking traditional constraints, with mass production expected between 2026 and 2030.

Intel’s glass-based substrate packaging technology has been in development for a decade and was unveiled at the 2023 Innovation Day in Silicon Valley, USA. Intel aims to achieve the goal of accommodating 1 trillion transistors within a single package by 2030 using advanced glass-based packaging.

The rise of the AI wave has driven the demand for accelerated computing, increasing the requirements for chip density. Intel argues that current substrate materials consume more power and are more prone to expansion and warpage compared to glass, which better aligns with future needs. Industry analysts have noted that TSMC also has similar solutions.

According to Intel, Glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

Glass substrates’ tolerance to higher temperatures also offers chip architects flexibility on how to set the design rules for power delivery and signal routing because it gives them the ability to seamlessly integrate optical interconnects, as well as embed inductors and capacitors into the glass at higher temperature processing.

According to a report from China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, and glass manufacturer Corning has introduced related products.

On the other hand, in a report by China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, with glass manufacturer Corning introducing related products.

(Photo credit: Intel)

According to a report by Taiwan’s Commercial Times, TSMC is facing a tight supply of advanced packaging capacity, with its Taichung factory ramping up equipment support at a rapid pace. Industry insiders have disclosed that TSMC’s annual production capacity for the backend CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging is only 150,000 to 300,000 units, falling short of customer demand by over 20%.

To address this shortfall, TSMC officially inaugurated its advanced packaging and testing Plant 6 in Zhunan in June. TSMC’s management has also committed to steadily increasing CoWoS production capacity each quarter, and third-party testing facilities are being actively engaged to bridge the gap.

It is worth noting that TSMC’s Longtan factory has traditionally been a key hub for CoWoS and InFO (Integrated Fan-Out) packaging, with a primary focus on InFO production at approximately 100,000 units per month and a smaller portion allocated to CoWoS. Although some of the InFO capacity has been relocated to the Southern Taiwan Science Park, Longtan’s physical space constraints continue to make Zhunan the primary location for CoWoS expansion. TSMC’s Taichung AP5 factory, on the other hand, is prioritizing WoS (Wafer-on-Substrate) expansion, with CoW (Chip-on-Wafer) expansion slated to commence next year. Many equipment suppliers have reportedly received urgent orders related to these expansion efforts.

Analysts estimate that this year’s overall CoWoS production will reach 110,000 units, doubling to 250,000 units next year. However, analysts caution that while TSMC currently dominates the CoWoS production landscape, other players are gradually entering the field. Therefore, it is crucial to monitor whether an oversupply situation may emerge in the mid-term next year.

(Photo credit: TSMC)