According to a report from Economic Daily News, Foxconn Group is advancing into the field of advanced packaging with a strategic alliance between Taiwan and Japan, focusing on the trending panel-level fan-out packaging (FOPLP). Following Innolux’s related developments in Taiwan, another of Foxconn’s invested companies, Sharp, has announced its entry into panel-level fan-out packaging in Japan, with production capacity expected in 2026.

Foxconn Group already possesses a comprehensive capability in the AI sector, and with the key advanced packaging technology now in place, they are fully mobilized. On the other hand, Sharp is undergoing a major transformation, which also benefits Foxconn— as its subsidiary Foxconn Technology is a major shareholder in Sharp, and Pan International is a partner with Sharp, both of which stand to gain from this transformation and provide support for it.

Pan International has previously collaborated with Sharp in areas such as wire harnesses, PCBs, and optical components, and has also acted as a distributor for Sharp’s panels and optoelectronic components. With Foxconn Chairman Young Liu concurrently serving as Sharp’s chairman, along with Sharp scaling down its panel business and expanding its semiconductor operations, there is significant interest in whether there will be new collaborations between the two companies.

Earlier, Sharp announced that it is partnering with Japanese electronic component manufacturer Aoi Electronics to advance into the field of advanced packaging. Reportedly, an agreement has been signed between Aoi, Sharp, and Sharp Display Technology, under which Aoi will utilize Sharp’s panel facilities to build a semiconductor back-end process production line. In 2024, Aoi will establish an advanced semiconductor panel packaging production line at Sharp’s Mie Plant, aiming for full-scale production by 2026 with a monthly capacity of 20,000 wafers.

Nikkei previously reported that Sharp continues to downsize its panel plants while expanding semiconductor production. Sharp noted that the advanced packaging production line will be used to produce Aoi’s FOLP. According to the agreement, the three companies are considering cooperation in the semiconductor back-end process to expedite the establishment of production lines and achieve full-scale production.

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(Photo credit: Foxconn)

TSMC’s advanced CoWoS packaging capacity is in severe shortage, and just as the new plant in the Chiayi Park of Southern Taiwan Science Park began construction for expansion, according to a report from Economic Daily News citing sources, it has stated that TSMC intends to build another advanced packaging plant in Pingtung, which is located in southern Taiwan, and is currently in the site selection phase.

Regarding these rumors, TSMC has not yet responded. The relevant authorities, the Taiwanese National Science and Technology Council, stated that they have not heard of this and emphasized that any information about new plant constructions should be released by the company itself.

Currently, TSMC’s in-house packaging and testing capacities are located in Longtan, Hsinchu Science Park, Zhunan, Central Taiwan Science Park, and Southern Taiwan Science Park, with a new plant under construction in the Chiayi Park of Southern Taiwan Science Park. However, construction of one plant in the Chiayi Park was recently suspended due to the possible discovery of a historical site, prompting TSMC to initiate the construction of a second plant in the area.

If the advanced packaging plant in Pingtung is established, TSMC will have seven advanced packaging and testing sites in Taiwan, spanning across Taoyuan, Hsinchu, Miaoli, Taichung, Chiayi, Tainan, and Pingtung.

TSMC Chairman C.C.Wei previously mentioned that the demand for CoWoS capacity exceeds supply. Despite continuous expansion, TSMC still cannot meet all customer needs. Consequently, TSMC has increased outsourcing to professional packaging and testing subcontractors. TSMC is striving to expand its advanced CoWoS packaging capacity, with a target to more than double its in-house capacity this year and continue efforts next year to narrow the gap between supply and demand.

Industry sources cited in Commercial Time’s previous report have further indicated that by the end of next year, TSMC’s monthly CoWoS capacity will be increased to 60,000 wafers. With growing orders and a steep learning curve, the annual capacity is expected to surpass 600,000 wafers next year. As the semiconductor industry advances into the Angstrom Era, the gap in TSMC’s advanced packaging capacity will gradually widen.

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(Photo credit: TSMC)

On June 21, ASE Group announced that ASE Semiconductor will collaborate with Hung Ching Construction to build a K28 plant in Kaohsiung. The project is expected to be completed in the fourth quarter of 2026 and will focus on end testing of advanced packaging processes, and high-performance computing for artificial intelligence (AI) chip.

ASE’s CFO Dong Hongsi introduced that for the K28 plant construction project, ASE Semiconductor will provide the land it held in Kaohsiung while Hung Ching Construction will provide fund support. The plant will have one basement level and seven above-ground floors. As to the rights and value distribution between the two parties, ASE Semiconductor and Hung Ching Construction will respectively hold a share of 22.24% and 77.76%. Upon completion, ASE Semiconductor or its subsidiaries will have the first purchase rights for Hung Ching Construction’s property ownership.

It was reported previously that as an important part of the company’s operational plans, ASE’s Kaohsiung plant had purchased land in Tashe for phased development in a bid to  address the demands for end testing of advanced packaging processes, AI chip high-performance computing, and heat dissipation needs. Phase one, the K27 plant, was completed in 2023, primarily setting up Flip Chip and IC testing production lines.

At a financial result briefing in February this year, ASE stated that to expand advanced packaging capacity, this year’s overall capital expenditure will increase by 40% to 50%, reaching a historical high. Of this, 65% will be allocated to packaging, especially advanced packaging projects, with over 60% used for packaging testing and 30% for electronic manufacturing services.

Moreover, ASE is optimistic about the potential of AI technology and expects AI revenue contributions to double to USD 500 million by the end of 2024 compared to 2023. AI-related revenue is expected to account for a single-digit percentage of the total ATM (Packaging and test) business this year, surpassing last year’s low single digit. And the industry anticipates that next year’s proportion could reach a high single-digit percentage.

Advanced packaging industry has been in high gear in recent years, and ASE has made significant investment in this area over the past two years. In February this year, Infineon and ASE announced that ASE would invest approximately TWD 2.1 billion to acquire Infineon’s two backend assembly and test plants in Philippines and South Korea. This acquisition aims to expand ASE’s  power chip module packaging & test and lead frame packaging for automotive and industrial automation applications, with the transaction expected to be completed by the end of 2Q24.

On January 19, ASE announced that its Malaysian subsidiary would invest MYR 69.696 million to acquire land use right in the Gardenia Tech Park in Penang, Malaysia to meet operational needs. Industry analysts believed this investment was primarily for expanding advanced packaging capacity. It was reported that ASE Semiconductor has been actively expanding its packaging and test capacity in Malaysia. In November 2022, its new factories 4 and 5 in Penang broke ground, with construction expected to be completed by 2025.

Additionally, in late December 2023, ASE Semiconductor announced that it had leased the 7th floors of both K21 and K22 buildings from ASE TEST in Kaohsiung’s Nanzi district to expand its packaging capacity. The industry believed that the intention was to increase its advanced packaging capacity for AI chip.

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• [News] ASE Sets Up New Facility in Kaohsiung for Advanced Packaging, Targeting Completion in 2026
• [News] ASE Expands Production at Kaohsiung Plant, Focusing on Advanced Packaging for AI Chips

According to a report from CNA, Taiwanese semiconductor testing and packaging giant ASE announced on June 21st that it will collaborate with Hung Ching Development & Construction Corporation to jointly build the K28 plant in Kaohsiung. Scheduled for completion in Q4 2026, the facility will reportedly focus on advanced packaging and final testing in order to meet the high-performance computing and cooling demands of AI chips.

ASE’s CFO Joseph Tung stated that ASE Semiconductor is planning for operational growth at its Kaohsiung facilities. To meet the demand for advanced packaging processes, high-performance computing for AI chips and cooling, the company is developing land in Dashe, Kaohsiung in two phases. The first phase, K27 plant, was completed and moved-in in 2023, while the K28 plant, the second phase, aims to be completed by Q4 2026.

As reported by CNA citing sources, ASE Kaohsiung Plant contributes approximately 20% to ASE Technology Holding Co., Ltd.’s total revenue. The plant specializes in providing services such as packaging, wafer bumping, probe testing, materials, and final testing. It has also developed several smart factories focusing on advanced processes, including Fan-out packaging, System-in-Package (SiP), wafer bumping, and Flip Chip packaging.

These technologies are primarily used in automotive, medical, IoT, high-speed computing, artificial intelligence, and application processor fields.

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According to a previous report from Nikkei citing sources, TSMC is rumored to be entering the fan-out panel-level packaging sector. As cited in a report from UDN, Intel and Samsung have also announced plans to invest in this area. With TSMC, the leading wafer foundry, joining the fray, the three semiconductor giants are set to compete in fan-out panel-level packaging.

TSMC stated yesterday that the company is closely monitoring the progress and development of advanced packaging technologies, including panel-level packaging technology.

Nikkei reported that in response to future AI demand trends, TSMC is collaborating with equipment and material suppliers to develop new advanced chip packaging technology. This technology uses a rectangular substrate for packaging, replacing the current traditional circular wafer, to accommodate more chipsets on a single wafer. The report further mentioned that TSMC’s research is still in its early stages and might take several years to commercialize, but it represents a significant technological shift.

Reportedly, TSMC previously considered the challenge of using rectangular substrates to be too high, requiring substantial time and effort from both the company and its suppliers, along with upgrades or replacements of many production tools and materials.

Nikkei  also mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

TSMC is expanding its advanced chip packaging capacity, with the expansion of the Taichung plant mainly for NVIDIA, while the Tainan plant is primarily for Amazon and its chip design partner Alchip Technologies.

TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips in two years.

Samsung and Intel have also recognized the aforementioned issues and are investing in next-generation advanced packaging technologies.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

Intel is planning to launch the industry’s first glass substrate solution for next-generation advanced packaging, with mass production scheduled between 2026 and 2030. Intel anticipates that data centers, AI, and graphics processing—markets that require larger volume packaging and higher-speed applications and workloads—will be the first to adopt this technology.

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(Photo credit: Intel)