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Taiwan’s semiconductor giant, TSMC, faces overwhelming demand for its 3nm technology, with major clients like Apple and NVIDIA fully allocate its production capacity.
According to a report from Commercial Times, orders are expected to be filled through 2026. Reportedly, TSMC is planning to raise its 3nm prices by over 5%, and advanced packaging prices are anticipated to increase by approximately 10% to 20% next year.
The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A. As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.
N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.
Per the industry sources cited by the same report, TSMC’s Zhunan advanced packaging plant (AP6), operational for a year now, has become Taiwan’s largest CoWoS base with the equipment moved into its AP6C plant. In the third quarter, CoWoS monthly production capacity is expected to double from 17,000 to 33,000 wafers.
Industry sources cited by the report further suggests that while AI accelerators do not use the most cutting-edge manufacturing processes, they rely heavily on advanced packaging technology. The ability of global semiconductor companies to secure more advanced packaging capacity from TSMC will determine their market penetration and control.
TSMC’s advanced packaging capacity is scarce, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. Broadcom, Amazon, and Marvell have also expressed strong interest in using advanced packaging processes. With gross margins close to 80%, NVIDIA is said to agree to price increases to secure more advanced packaging capacity, thereby distancing itself from competitors.
Previously, NVIDIA CEO Jensen Huang emphasized that TSMC is not just manufacturing wafers but also handling numerous supply chain issues. He also agreed that the current pricing is too low and would support TSMC’s price increase actions.
The industry sources cited by Commercial Times have indicated that TSMC plans to add CoWoS-related equipment by the third quarter and has requested equipment manufacturers to dispatch more engineers to fully staff its Longtan AP3, Zhunan AP6, and Central Taiwan Science Park AP5 plants.
In addition to Zhunan’s AP6C, the Central Taiwan Science Park plant, which originally only handled the latter stages of oS, will also gradually transition to CoW processes. Meanwhile, the Chiayi site is in the land preparation stage and is expected to progress faster than Tongluo.
Reportedly, industry sources further reveal that the prices for advanced process nodes such as 3nm and 5nm will also be adjusted. Particularly, strong demand for 3nm orders in the second half of the year is expected to drive utilization rates to near full capacity, extending through 2025. The 5nm process is experiencing similar demand dynamics, driven by AI needs.
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With high demand for AI chips from major players like NVIDIA and AMD, the capacity for advanced packaging falls short of meeting demand. Industry sources cited in a report from the Economic Daily News indicate that TSMC’s new CoWoS facility in the Southern Taiwan Science Park in Chiayi is now undergoing environmental impact assessments, prompting the commencement of equipment procurement.
Additionally, considering the insufficiency of planned CoWoS facilities in the Chiayi park, TSMC is reportedly sending representatives to survey additional land for potential expansion.
Regarding these developments, TSMC stated on June 11 that they do not comment on market rumors.
With the rapid development of AI applications, the demand for advanced packaging in the chip market has surged. TSMC, serving as the major foundry partner for tech giants like NVIDIA and AMD in AI chip production, has faced continuous high demand for advanced packaging capacity for some time. The company has been actively expanding related capacity and is now venturing into building a new CoWoS facility in the Southern Taiwan Science Park in Chiayi.
According to the information previously announced by the Chiayi County government, TSMC’s advanced packaging facility will occupy approximately 20 hectares in the Southern Taiwan Science Park, with the first facility covering around 12 hectares. The first advanced packaging fab is expected to be completed by the end of 2026, creating 3,000 job opportunities. TSMC initially plans to build two advanced packaging facilities in the area.
According to official information from TSMC, its backend test and packaging facilities include the Hsinchu Advanced Backend Fab 1, Southern Taiwan Science Park Advanced Backend Fab 2, Longtan Advanced Backend Fab 3, Central Taiwan Science Park Backend Advanced Fab 5, and Miaoli Zhunan Advanced Backend Fab 6.
Industry sources cited by the same report from the Economic Daily News further indicate that advanced packaging-related equipment is currently being gradually supplied to TSMC’s Zhunan, Central Taiwan, and Southern Taiwan fabs, with shipments to the Chiayi facility expected to commence from the third quarter of next year.
TSMC Chairman C.C. Wei previously mentioned that despite their efforts to increase capacity, the strong demand from customers has led to an insufficient supply, which has led to outsourcing to specialized packaging and testing foundries. He emphasized TSMC’s ongoing expansion of CoWoS advanced packaging capacity, with the goal of doubling their in-house capacity growth this year and continuing efforts into next year to narrow the gap between supply and demand.
TSMC has integrated its advanced packaging-related technologies into the “3DFabric” platform, allowing customers to select and configure according to their needs. The front-end technologies include System on Integrated Chip (SoIC), while the back-end assembly and testing technologies include Integrated Fan-Out (InFO) and the CoWoS series family.
In June 2023, TSMC announced the official opening of its Advanced Backend Fab 6 located in the Zhunan Science Park, becoming its first fully automated advanced packaging and testing facility to realize integrated front-end to back-end processes and testing services under the 3DFabric platform.
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With the flourishing of AI applications, two major AI giants, NVIDIA and AMD, are fully committed to the high-performance computing (HPC) market. It’s reported by the Economic Daily News that they have secured TSMC’s advanced packaging capacity for CoWoS and SoIC packaging through this year and the next, bolstering TSMC’s AI-related business orders.
TSMC holds a highly positive outlook on the momentum brought by AI-related applications. During the April earnings call, CEO C.C. Wei revised the visibility of AI orders and their revenue contribution, extending the visibility from the original expectation of 2027 to 2028.
TSMC anticipates that revenue contribution from server AI processors will more than double this year, accounting for a low-teens percentage of the company’s total revenue in 2024. It also expects a 50% compound annual growth rate for server AI processors over the next five years, with these processors projected to contribute over 20% to TSMC’s revenue by 2028.
Per the industry sources cited by the same report from Economic Daily News, they have indicated that the strong demand for AI has led to a fierce competition among the four global cloud service giants, including Amazon AWS, Microsoft, Google, and Meta, to bolster their AI server arsenal. This has resulted in a supply shortage for AI chips from major manufacturers like NVIDIA and AMD.
Consequently, these companies have heavily invested in TSMC’s advanced process and packaging capabilities to meet the substantial order demands from cloud service providers. TSMC’s advanced packaging capacity, including CoWoS and SoIC, for 2024 and 2025 has been fully booked.
To address the massive demand from customers, TSMC is actively expanding its advanced packaging capacity. Industry sources cited by the report have estimated that by the end of this year, TSMC’s CoWoS monthly capacity could reach between 45,000 to 50,000 units, representing a significant increase from the 15,000 units in 2023. By the end of 2025, CoWoS monthly capacity is expected to reach a new peak of 50,000 units.
Regarding SoIC, it is anticipated that the monthly capacity by the end of this year could reach five to six thousand units, representing a multiple-fold increase from the 2,000 units at the end of 2023. Furthermore, by the end of 2025, the monthly capacity is expected to surge to a scale of 10,000 units.
It is understood that NVIDIA’s mainstay H100 chip currently in mass production utilizes TSMC’s 4-nanometer process and adopts CoWoS advanced packaging. Additionally, it supplies customers with SK Hynix’s High Bandwidth Memory (HBM) in a 2.5D packaging form.
As for NVIDIA’s next-generation Blackwell architecture AI chips, including the B100, B200, and the GB200 with Grace CPU, although they also utilize TSMC’s 4-nanometer process, they are produced using an enhanced version known as N4P. The production for the B100, per a previous report from TechNews, is slated for the fourth quarter of this year, with mass production expected in the first half of next year.
Additionally, they are equipped with higher-capacity and updated specifications of HBM3e high-bandwidth memory. Consequently, their computational capabilities will see a multiple-fold increase compared to the H100 series.
On the other hand, AMD’s MI300 series AI accelerators are manufactured using TSMC’s 5-nanometer and 6-nanometer processes. Unlike NVIDIA, AMD adopts TSMC’s SoIC advanced packaging to vertically integrate CPU and GPU dies before employing CoWoS advanced packaging with HBM. Hence, the production process involves an additional step of advanced packaging complexity with the SoIC process.
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Powerchip Semiconductor Manufacturing Corporation (PSMC) held the inauguration ceremony for its new Tongluo plant on May 2nd. This investment project, totaling over NTD 300 billion for a 12-inch fab, has completed the installation of its initial equipment and commenced trial production. According to a report from Commercial Times, it will serve as PSMC’s primary platform for advancing process technology and pursuing orders from large international clients.
Additionally, PSMC has ventured into advanced CoWoS packaging, primarily producing Silicon Interposers, with mass production expected in the second half of the year and a monthly capacity of several thousand units.
Frank Huang, Chairman of PSMC, stated that construction of the new Tongluo plant began in March 2021. Despite challenges posed by the pandemic, the plant was completed and commenced operations after a three-year period.
As of now, the investment in this 12-inch fab project has exceeded NTD 80 billion, underscoring the significant time, technology, and financial requirements for establishing new semiconductor production capacity. Fortunately, the company made swift decisions and took action to build the plant. Otherwise, with the recent international inflation driving up costs of various raw materials, the construction costs of this new plant would undoubtedly be even higher.
The land area of Powerchip Semiconductor Manufacturing Corporation’s Tongluo plant exceeds 110,000 square meters. The first phase of the newly completed plant comprises a cleanroom spanning 28,000 square meters. It is projected to house 12-inch wafer production lines for 55nm, 40nm, and 28nm nodes with a monthly capacity of 50,000 units. In the future, as the business grows, the company can still construct a second phase of the plant on the Tongluo site to continue advancing its 2x nanometer technology.
Frank Huang indicated that the first 12-inch fab in Taiwan was established by the Powerchip group. To date, they have built eight 12-inch fabs and plan to construct four more in the future. Some of these fabs will adopt the “Fab IP” technology licensing model. For example, the collaboration with Tata Group in India operates under this model.
According to a previous report from TechNews, Frank Huang believes that IP transfer will also become one of the important sources of revenue in the future. “Up to 7-8 countries have approached PSMC,” including Vietnam, Thailand, India, Saudi Arabia, France, Poland, Lithuania, and others, showing interest in investing in fabs, indicating optimism for PSMC’s future Fab IP operating model.
PSMC’s Fab IP strategy, according to the same report, leverages its long-term accumulated experience in plant construction and semiconductor manufacturing technology to assist other countries, extending from Japan and India to countries in the Middle East and Europe, in building semiconductor plants while earning royalties for technology transfers.
Looking ahead to the second half of the year, Frank Huang indicated that the current issue lies in the less-than-stellar performance of the economies of the United States and China. While the United States is showing relatively better performance in AI and technology, China’s performance is not as strong.
Huang believes that after the fourth quarter of this year, there is a chance for accelerated deployment of AI application products such as smartphones, PCs, and notebooks. With the explosive demand brought about by AI, 2025 is expected to be a very good year for the semiconductor industry, and PSMC has already seized the opportunity.
In addition, PSMC also mentioned that since last year, there has been a continuous tight supply of advanced CoWoS packaging. In response to the demands of global chip clients, the company has also ventured into CoWoS-related businesses, primarily providing the Silicon Interposer needed for advanced CoWoS packaging. Currently in the validation stage, mass production is expected to commence in the second half of the year, with an initial monthly capacity of several thousand units.
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The demand for AI computing power is skyrocketing, with advanced packaging capacity becoming key. As per a report from Commercial Times citing industry sources, it has pointed out that TSMC is focusing on the growth potential of advanced packaging.
Southern Taiwan Science Park, Central Taiwan Science Park and Chiayi Science Park are all undergoing expansion. The Chiayi Science Park, approved this year, is set to construct two advanced packaging factories ahead of schedule. Phase one of Chiayi Science Park is scheduled to break ground this quarter, with first tool-in slated for the second half of next year. Phase two of Chiayi Science Park is expected to start construction in the second quarter of next year, with first tool-in planned for the first quarter of 2027, continuing to expand its share in the AI and HPC markets.
Advanced packaging technology achieves performance enhancement by stacking, thus increasing the density of inputs/outputs. TSMC recently unveiled numerous next-generation advanced packaging solutions, involving various new technologies and processes, including CoWoS-R and SoW.
The development of advanced packaging technology holds significant importance for the advancement of the chip industry. TSMC’s innovative solutions bring revolutionary wafer-level performance advantages, meeting the future AI demands of ultra-large-scale data centers.
Industry sources cited by the same report has stated that TSMC’s introduction of system-level wafer technology enables 12-inch wafers to accommodate a large number of chips, providing greater computational power while significantly reducing the space required in data centers.
This advancement also increases the power efficiency. Among these, the first commercially available SoW product utilizes an integrated fan-out (InFO) technology primarily for logic chips. Meanwhile, the stacked chip version employing CoWoS technology is expected to be ready by 2027.
As stacking technology advances, the size of AI chips continues to grow, with a single wafer potentially yielding fewer than ten super chips. Packaging capacity becomes crucial in this scenario. The industry sources cited in Commercial Time’s report also note that TSMC’s Longtan Advanced Packaging plant with a monthly capacity of 20,000 wafers is already at full capacity. The Zhunan AP6 plant is currently the main focus of expansion efforts, with equipment installation expected to ramp up in the fourth quarter at the Central Taiwan Science Park facility, accelerating capacity preparation.
TSMC’s SoIC has emerged as a leading solution for 3D chip stacking. AMD is the inaugural customer for SoIC, with its MI300 utilizing SoIC paired with CoWoS.
Apple has also officially entered the generative AI battlefield. It’s noted by the sources as per the same report that Apple’s first 3D packaged SoIC product will be its ARM-based CPU for AI servers, codenamed M4 Plus or M4 Ultra, expected to debut as early as the second half of next year. The 3D packaged SoIC technology is projected to be further extended to consumer-grade MacBook M series processors by 2026.
NVIDIA, on the other hand, is reportedly set to launch the R100 in the second half of next year, utilizing chiplet and the CoWoS-L packaging architecture. It’s not until 2026 that they will officially introduce the X100 (tentative name), which adopts a 3D packaging solution incorporating SoIC and CoWoS-L.
As per a recent report from MoneyDJ citing industry sources, the SoIC technology is still in its early stages, with monthly production capacity expected to reach around 2,000 wafers by the end of this year. There are prospects for this capacity to double this year and potentially exceed 10,000 wafers by 2027.
With support from major players like AMD, Apple, and NVIDIA, TSMC’s expansion in SoIC is viewed as confident, securing future orders for high-end chip manufacturing and advanced packaging.
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