In a bid to catch up with leading players like TSMC, the South Korean government is said to have approved a national-level initiative aimed at actively promoting the development of advanced chip packaging technologies, according to a report from South Korean media outlet TheElec.

Citing anonymous sources, the report on April 30th indicates that the feasibility of the aforementioned plan has passed the preliminary examination conducted by the Korea Institute of S&T Evaluation and Planning (KISTEP).

According to reports, the preliminary review targeted a national-level project with a value exceeding KRW 50 billion, with direct government sponsorship exceeding KRW 30 billion. Such projects rarely pass the review in one go, but the aforementioned chip packaging case is an exception.

Most of the reviewers at KISTEP have reportedly reached a consensus, recognizing the necessity of the project to catch up with leaders in advanced packaging like Taiwan’s TSMC, making South Korea a frontrunner.

As per TrendForce’s previous report, by 2027, Korea’s share in advanced process capacity is originally expected to reach 11.5%, with room for further growth.

However, the budget for the 7-year project has been reduced from the original KRW 500 billion to KRW 206.8 billion. After passing the preliminary feasibility review, the project is expected to be formally announced later this year (2024) and is scheduled to commence implementation next year.

Cited by the same report from TheElec, a source involved in the project stated that the budget cut was entirely expected, but the project’s single-pass approval is indeed noteworthy, indicating the government’s deep understanding of the importance of chip packaging.

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(Photo credit: TSMC)

Per a report from TechNews, during Intel’s earnings call last week, CEO Pat Gelsinger stated that the supply of Core Ultra processors in the second quarter is limited due to insufficient wafer-level assembly capacity.

Gelsinger mentioned in the meeting that with the increasing demand for AI PCs and customers continually adding processor orders to Intel due to Windows update cycles, Intel’s AI PC CPU shipments for 2024 are expected to surpass the originally set target of 40 million units. In response, Intel is actively ramping up production to meet customer demand, with the current supply bottleneck primarily concentrated in the backend wafer-level assembly.

Wafer-level assembly is a technology where packaging is done on wafers before they are cut into chips, widely utilized in processors like Meteor Lake and future Core Ultra processors. However, in the face of overwhelming demand, this production bottleneck has led Intel’s Consumer Computing Division to anticipate second-quarter revenue to be roughly equivalent to that of the first quarter, around USD 7.5 billion.

To address this issue, Intel is actively enhancing its wafer-level assembly capacity to meet the growing orders. It is expected that the current tight situation will be alleviated in the second half of 2024, facilitating further revenue growth for the Consumer Computing Division.

As per previous report by Economic Daily News, Intel has advanced packaging capacity in Oregon and New Mexico in the United States and is actively expanding its advanced packaging capabilities in its new facility in Penang. It is noteworthy that Intel once stated its intention to offer customers the option to only use its advanced packaging solutions, expected to provide customers with greater production flexibility.

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(Photo credit: Intel)

Amid NVIDIA’s leadership in the AI wave, demand for CoWoS (Chip-on-Wafer-on-Substrate) has tripled, driving TSMC to aggressively expand CoWoS capacity, with a corresponding surge in demand for System-in-Integrated-Circuit (SoIC) solutions.

According to a report from MoneyDJ citing industry sources, it has suggested that in addition to AMD, which has already implemented SoIC in production, Apple is conducting limited trial production. Furthermore, collaborations are underway with NVIDIA and Broadcom, indicating that SoIC is poised to become TSMC’s next advanced packaging solution following CoWoS.

TSMC’s SoIC is the industry’s first high-density 3D chip stacking technology, enabling heterogeneous integration of chips with different sizes, functionalities, and nodes using Chip on Wafer packaging. Currently, production takes place at the AP6 assembly and testing facility in Zhunan, Taiwan. It’s rumored that the planned advanced packaging facility in Chiayi, Taiwan will include not only two CoWoS plants but also an SoIC facility.

AMD is the first customer to adopt SoIC technology, with its latest MI300 chip using SoIC combined with CoWoS solution. Apple, TSMC’s primary customer, is reportedly interested in SoIC and plans to incorporate it with Hybrid molding technology for Mac products. Small-scale trials are currently underway, with mass production anticipated between 2025 and 2026. NVIDIA and Broadcom are also collaborating in this field.

As per the same report citing industry sources, the SoIC technology is still in its early stages, with monthly production capacity expected to reach around 2,000 wafers by the end of this year. There are prospects for this capacity to double this year and potentially exceed 10,000 wafers by 2027.

With support from major players like AMD, Apple, and NVIDIA, TSMC’s expansion in SoIC is viewed as confident, securing future orders for high-end chip manufacturing and advanced packaging.

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(Photo credit: TSMC)

According to a report from South Korean media outlet TheElec, Samsung’s Advanced Package (AVP) team has reportedly secured an advanced packaging order for NVIDIA’s AI chip, paving the way for future supply of NVIDIA’s high-bandwidth memory (HBM) chips.

The report, citing sources, reveals that Samsung Electronics’ Advanced Packaging team will provide interposer and 2.5D packaging technology for packaging NVIDIA’s AI processors. However, the HBM and GPU chips used in these NVIDIA AI processors will be supplied by others.

2.5D packaging technology enables the horizontal integration of chips like CPUs, GPUs, and HBMs on an interposer. Processors such as NVIDIA’s A100, H100, and Intel’s Gaudi all utilize this technology for packaging.

TSMC’s CoWoS advanced packaging facility utilizes 2.5D packaging technology, while Samsung Electronics employs their iCube technology, which also falls under the category of 2.5D packaging.

Over the past year, Samsung Electronics has been expanding its advanced packaging division by increasing personnel and developing its own interposer technology. They have also procured a large amount of 2.5D packaging equipment from Japanese semiconductor equipment suppliers such as Shinkawa and others.

The same report from TheElec also revealed that in the future, stacking eight HBM chips on a 12-inch wafer will require the use of 16 interposers. Therefore, Samsung Electronics is actively working to increase its silicon interposer production capacity.

Although Samsung Electronics has declined to comment on the rumors regarding NVIDIA’s packaging orders, industry speculation suggests a connection to insufficient capacity at TSMC’s CoWoS, compounded by recent earthquakes in Taiwan potentially further impacting TSMC’s CoWoS capacity. This has led to expectations of future growth in orders for Samsung Electronics’ Advanced Packaging Division.

Samsung Electronics’ plant located in Cheonan, South Korea, is where the company’s Advanced Packaging team is based. Recently, the production capacity at the Cheonan plant has reportedly been ramped up to full utilization, which is believed by industry observers to be one of the possible reasons why Samsung secured NVIDIA’s advanced packaging orders.

Previously reported by The Korea Times, Samsung Co-CEO Kye-Hyun Kyung stated that he expects the results of Samsung’s investment to come out in earnest from the second half of this year.

Kyung further noted that for a future generation of HBM chips called HBM4, likely to be released in 2025 with more customised designs, Samsung will take advantage of having memory chips, chip contract manufacturing and chip design businesses under one roof to satisfy customer needs.

TrendForce’s latest report reveals that in 2023, global foundry revenues hit US$117.47 billion, with TSMC accounting for close to 60% of the market share, while Samsung held approximately 11%.

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(Photo credit: Samsung)

SK Hynix is rumored planning to build an advanced packaging fab worth USD 4 billion in West Lafayette, Indiana. According to a report from The Wall Street Journal, it is expected to commence operations by 2028, creating up to 1,000 job opportunities. This initiative may receive support in the form of state and federal tax incentives.

As reported by The Wall Street Journal and Tom’s Hardware, SK Hynix’s investment aims to enhance its capabilities in advanced semiconductor packaging, with a particular emphasis on manufacturing High-Bandwidth Memory (HBM).

Considering a potential capital expenditure of USD 4 billion for the construction, per Tom’s Hardware, if the project proceeds, it will become one of the largest advanced packaging facilities globally. Hence, government support is crucial, with expectations of tax incentives from both state and federal levels in the US.

SK Hynix, a supplier of HBM memory for NVIDIA, is eyeing enhanced capabilities in advanced chip packaging, particularly crucial for manufacturing HBM. The recent NVIDIA Blackwell B200, with each GPU utilizing 8 HBM3e chips, has also underscored SK Hynix’s role in the critical components supply chain for the AI industry.

The recent CHIPS and Science Act allocated USD 8.5 billion to Intel, enhancing US semiconductor competitiveness. SK Hynix’s plan to build a fab in Indiana is a significant stride, fostering US semiconductor growth.

However, US subsidies for chip manufacturing and packaging have been slow, with only three American companies currently benefiting, including BAE Systems, GlobalFoundries, and Microchip Technology.

Reportedly, SK Hynix’s plan remains more of an intention statement than a finalized deal, and whether it proceeds to the construction phase remains to be seen.

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(Photo credit: SK Hynix)