Amid the AI boom driving a surge in demand for advanced packaging, South Korean semiconductor giant Samsung Electronics is aggressively entering the advanced packaging arena. On the 20th, it announced its ambitions to achieve record-high revenue in advanced packaging this year, aiming to surpass the USD 100 million mark.

According to reports from Reuters and The Korea Times, Samsung’s annual shareholders’ meeting took place on March 20th.

During the meeting, Han Jong-hee, the vice chairman of the company, stated as follows: “Although the macroeconomic environment is expected to be uncertain this year, we see an opportunity for increased growth through next-generation technology innovation.”

“Samsung plans to apply AI to all devices, including smartphones, foldable devices, accessories and extended reality (XR), to provide customers with a new experience where generative AI and on-device AI unfold,” Han added.

Samsung established the Advanced Package Business Team under the Device Solutions business group in December last year. Samsung Co-CEO Kye-Hyun Kyung stated that he expects the results of Samsung’s investment to come out in earnest from the second half of this year.

Kyung further noted that for a future generation of HBM chips called HBM4, likely to be released in 2025 with more customised designs, Samsung will take advantage of having memory chips, chip contract manufacturing and chip design businesses under one roof to satisfy customer needs.

According to a previous report from TrendForce, Samsung led the pack with the highest revenue growth among the top manufacturers in Q4 as it jumped 50% QoQ to hit $7.95 billion, largely due to a surge in 1alpha nm DDR5 shipments, boosting server DRAM shipments by over 60%. In the fourth quarter of last year, Samsung secured a market share of 45.5% in DRAM chips.

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(Photo credit: Samsung)

Driven by the AI chip wave, “advanced packaging” emerges as the hottest technology in the semiconductor industry. Its significance extends beyond computational power demands, as the escalating cost of semiconductor processes and the limits of Moore’s Law make the “integration capability” of advanced packaging a crucial weapon for industry players to break through.

According to a report from TechNews, TSMC, Intel, and Samsung have all been deeply involved in advanced packaging for many years and have already introduced corresponding solutions. However, these semiconductor giants are not only focused on this aspect.

In addition to their own technologies, they are actively fostering supply chains, setting standards, and building ecosystems. By accelerating the development of advanced packaging technology, they are also laying the groundwork for their future influence.

Intel, for instance, has chosen to start with standardization by proposing the Universal Chiplet Interconnect Express (UCIe) alliance. Through open specifications and standardized connections, the protocol directly adopts mature standards like PCI Express (PCIe) and the recently developed Compute Express Link (CXL).

The reason for starting with chiplet technology is that in recent years, more and more semiconductor companies have discovered that designing chips using Chiplet architecture and integrating them through advanced packaging technology is more cost-effective than traditional System-on-Chip (SoC) approaches.

Therefore, Intel’s focus on connecting chiplets through standards like UCIe is aimed at providing a standardized interface stack for complete chiplet integration. UCIe supports 2D, 2.5D, and bridge packaging, with future development expected to include support for 3D packaging as well.

Intel’s Packaging Test Technology Development Department’s Senior Chief Engineer, Zhiguo Qian, directly involved in the UCIe Alliance, emphasizes that advanced packaging has become a crucial aspect of semiconductor development, particularly in ensuring the continuation of Moore’s Law.

Qian further points out that when considering the impact of the UCIe standard on the advanced packaging industry, it indeed establishes a standard for interconnecting chiplets within SoCs. This was the original intent behind Intel’s promotion of the UCIe standard alliance.

Currently, advanced packaging is mostly divided into different structures like 2.5D and 3D, and some even classify it as 2.1D or 2.2D, showcasing diverse structural designs across the industry.

However, within these structures, each company has its own proprietary interface solutions, and some even offer multiple solutions. Therefore, to meet customer demands, these standard interconnections must not only be at the forefront of technology but also be compatible with various standards that are open and do not incur any licensing fees.

On the other hand, the UCIe alliance has established various standards, such as the required packaging architectures and interface wiring designs, to achieve the desired performance levels. These standards provide guidelines for customers seeking advanced packaging solutions. By adhering to UCIe standards, customers can anticipate the performance of their chips, without the need for trial and error(in the IC designing stage).

Source: Intel

Currently, companies participating in the UCIe alliance include Qualcomm, AMD, Arm, NVIDIA, TSMC, ASE Group, Winbond Electronics, and Applied Materials, among others, along with semiconductor giants like Samsung. Additionally, Google Cloud, Microsoft, and Meta are members, alongside over 120 other companies.

• TSMC Propels 3D Fabric Alliance

TSMC is also focused on ecosystem development, as evidenced by its announcement of the 3DFabric Alliance within the Open Innovation Platform (OIP) during the 2022 Open Innovation Platform Ecosystem Forum.

In fact, the 3DFabric Alliance is built upon TSMC’s 3DFabric technology introduced in 2020. This technology encompasses a comprehensive solution ranging from advanced processes to silicon stacking and advanced packaging technologies such as CoWoS and InFO.

With an established customer base for its 3DFabric technology, TSMC expanded it into an alliance in 2022. The goal is to assist customers in achieving rapid implementation of chip and system-level innovations while strengthening TSMC’s influence in advanced packaging.

The 3DFabric Alliance marks TSMC’s sixth open innovation platform alliance and is the semiconductor industry’s first alliance aimed at accelerating innovation and enhancing the 3D Integrated Circuit (3D IC) ecosystem in collaboration with partners.

This alliance includes companies in electronic design automation (EDA), silicon intellectual property (IP), design center alliances (DCA)/value chain alliances (VCA), memory, outsourced packaging testing (OSAT), and substrate and testing. Members include Ansys, Cadence, Siemens, ARM, Micron, Samsung, SK Hynix, Amkor, ASE, Advantest, and more.

Source: TSMC

In addition to establishing the alliance, TSMC also introduced the 3Dblox standard during the alliance’s inception. This standard integrates the design ecosystem with validated EDA tools and processes to support 3DFabric technology.

The purpose of this standard is to break the complexity of 3D IC design caused by each EDA supplier using its preferred language. Through the modular 3Dblox standard, key physical stacking and logic connection information in 3D IC design are standardized in a single format, simplifying input and significantly enhancing interoperability among different tools in 3D IC design.

From Intel’s UCIe standard to TSMC’s 3DFabric alliance and 3Dblox standard, it’s evident that in the era of advanced packaging, the key to solidifying the positions and market shares of semiconductor giants lies not only in their individual technological breakthroughs but also in their ability to coordinate and integrate the upstream and downstream industries.

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(Photo credit: TSMC)

“It is not the shortage of AI chips, it is the shortage of our CoWoS capacity,” replied TSMC Chairman Mark Liu during an interview in September last year, propelling this technology that TSMC had quietly cultivated for over a decade into a global spotlight.

As per a report from TechNews, the hardware demand sparked by generative AI has also led to “advanced packaging” becoming not only a hot keyword pursued by global investors but also a prominent feature of the semiconductor industry. From foundries and memory manufacturers to OASTs, all are actively involved in the research and capacity expansion of advanced packaging technologies.

TSMC, the leading force in the advanced packaging market, has repeatedly emphasized its efforts to expand capacity during its earnings call, including capacity expansions in Zhunan and Hsinchu, and even the possibility of constructing advanced packaging facilities in Chiayi.

Intel’s strategic moves also underscore its emphasis on the development of advanced packaging. Intel’s new plant completed in Penang, Malaysia in 2023 is aimed at establishing advanced packaging capacity.

Leading packaging and testing company, ASE Technology Holding, has also actively participated in the competition for advanced packaging. Apart from its subsidiary, Siliconware Precision Industries (SPIL), which is already a supplier for the backend packaging of CoWoS, ASE Technology Holding is also expanding advanced packaging capacity at its facility in Kaohsiung.

Memory manufacturers are also aggressively ramping up their advanced packaging capacity. SK Hynix, which exclusively supplies HBM for NVIDIA AI chips, recently announced plans to invest USD 1 billion in the development of advanced packaging. They view advanced packaging as the “future focus of semiconductor development for the next 50 years.

Advanced Packaging: Over a Decade of Development

In fact, advanced packaging is not a new concept. Tracing the history of packaging technology, the year 2000 undoubtedly marked a turning point. From this year onwards, packaging technology shifted from traditional wire bonding and flip-chip methods to “wafer-level packaging,” where most or all packaging and testing processes are conducted on the wafer itself.

The 2.5D packaging, which gained significant attention after 2023, actually emerged as early as 2010. However, due to cost concerns, the number of manufacturers adopting this technology was relatively limited, with a focus on high-performance computing chips.

Chiang Shang-yi, the Chief Strategy Officer of Foxconn Semiconductor, recalled the initial lack of interest in CoWoS technology, which even led to him being regarded as a “joke” within the company( TSMC) for proposing advanced packaging. He also revealed that the first company willing to adopt the costly CoWoS technology was actually Huawei.

▲ Semiconductor Packaging Technology Evolution compiled by McKinsey, Accelerated Technological Evolution after 2000 (Source: McKinsey)

Compared to 2D packaging technology, 2.5D packaging involves placing an intermediate layer between the chip and the IC substrate and stacking different chips in parallel. TSMC’s CoWoS has become synonymous with 2.5D packaging, where a silicon interposer layer is inserted between the chip and the SiP substrate, and metal layers are connected using Through-Silicon Vias (TSVs) to overcome the density limitations of SiP substrates, which previously restricted the number of chips.

Despite TSMC’s dominance, Intel, with its extensive technical expertise in CPU packaging, cannot be underestimated. In the 2.5D packaging battlefield, Intel employs EMIB technology as its strategy. Unlike CoWoS, EMIB does not utilize a silicon interposer layer.

Instead, its key feature lies in the “Silicon Bridge,” buried within the packaging substrate, which connects the bare dies. Intel believes that EMIB offers cost advantages compared to solutions using large silicon interposer layers.

In recent years, Samsung, which has been actively cultivating the semiconductor foundry market, has also ventured into the 2.5D packaging arena. Their proprietary I-Cube technology has traditionally targeted applications in High-Performance Computing (HPC) chips. When Samsung introduced I-Cube4 in 2021, it emphasized the integration of multiple logic dies and HBM placed on a silicon interposer layer, enabling heterogeneous integration into a single chip.

As Moore’s Law approaches its limits and the massive computational demands triggered by generative AI continue to surge, coupled with the trend towards lighter, thinner, and smaller end products, chips are inevitably evolving towards more transistors, greater computational power, and lower power consumption performance.

Therefore, the transition of packaging technology from 2.5D to 3D is undoubtedly an inevitable development.

The difference between 3D and 2.5D packaging lies in the stacking method. In 2.5D packaging, chips are stacked parallelly on an intermediate layer, while in 3D packaging, chips are stacked vertically in a three-dimensional manner.

The advantage of 3D packaging lies in its ability to create more space for transistors within a chip through stacking, shorten the distance between different bare dies significantly, enhance transmission efficiency, and reduce power consumption during transmission.

TSMC, Intel, and Samsung Racing for 3D Packaging Technology

TSMC’s positioning in 3D IC technology is undeniable. Its SoIC technology adopts the wafer-to-wafer bonding technique. SoIC integrates homogeneous and heterogeneous small dies into a single chip, with smaller dimensions and a thinner profile. It can be integrated into 2.5D CoWoS or InFO. From an external perspective, SoIC resembles a universal SoC chip but integrates various functions heterogeneously.

Intel’s layout in 3D packaging revolves around its 3D Foveros technology. Structurally, the bottom layer comprises a packaging substrate, with a bottom wafer placed on top serving as an intermediate layer. Within this intermediate layer, numerous TSVs (Through-Silicon Vias) are present, facilitating connections between the upper chips, modules, and other parts of the system to achieve transmission purposes.

Samsung’s X-Cube 3D packaging technology utilizes TSV processes. Currently, Samsung’s X-Cube test chips can stack the SRAM layer on top of the logic layer, interconnected via TSVs, employing its 7nm EUV process technology.

TSMC’s Comprehensive Ecosystem Strategy

Currently dominating the advanced packaging market, thanks to its acquisition of large contracts for manufacturing NVIDIA AI chips, TSMC is not only continuing to develop more advanced packaging technologies but is also actively promoting its 3D Fabric platform.

In addition to incorporating the three key packaging technologies CoWoS, InFo, and SoIC, this platform has expanded into an industry alliance. It includes participation from EDA, IP, DCA/VCA, memory, packaging and testing suppliers, as well as substrate and testing vendors. The goal is to create a complete 3D Fabric ecosystem, strengthen innovation, and enhance customer adoption willingness.

This alliance has attracted active participation from heavyweight players in the semiconductor upstream supply chain. Even companies traditionally seen as competitors in the packaging and testing sector, such as Amkor, ASE Technology Holding, and Siliconware Precision Industries (SPIL), are members. The comprehensive supply chain has become a significant advantage for TSMC in providing advanced packaging contract manufacturing services.

▲ TSMC’s 3D Fabric Alliance members, including major players from EDA to packaging and testing companies. (Image Source: TSMC)

In comparison, Intel, despite its robust technological expertise developed over many years and its proposition to independently provide wafer manufacturing or testing services, faces a disadvantage in expanding its market share in advanced packaging due to its lack of experience in the foundry market.

On the other hand, Samsung, compared to TSMC, is constrained by its yield issues in advanced processes. This limitation leads IC design companies to prioritize foundries with more stable yields when considering outsourcing comprehensive manufacturing services.

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(Photo credit: TSMC)

South Korean memory giant SK Hynix is significantly investing in advanced chip packaging, aiming to capture more demand for High Bandwidth Memory (HBM), a vital component driving the burgeoning AI market.

According to Bloomberg’s report, Lee Kang-Wook, currently leading SK Hynix’s packaging research and development, stated that the company is investing over USD 1 billion in South Korea to expand and enhance the final steps of its chip manufacturing process.

“The first 50 years of the semiconductor industry has been about the front-end, or the design and fabrication of the chips themselves,” Lee Kang-Wook expressed in an interview with Bloomberg. “But the next 50 years is going to be all about the back-end, or packaging.”

The same report further indicates that the packaging upgrade will help reduce power consumption, enhance performance, and maintain SK Hynix’s leadership position in the HBM market.

Recent market trends also highlight the crucial role of advanced packaging in the manufacturing of HBM products. According to a recent report by South Korean media DealSite, the complex architecture of HBM has resulted in difficulties for manufacturers like Micron and SK Hynix to meet NVIDIA’s testing standards.

The yield of HBM is closely tied to the complexity of its stacking architecture, which involves multiple memory layers and Through-Silicon Via (TSV) technology for inter-layer connections. These intricate techniques increase the probability of process defects, potentially leading to lower yields compared to simpler memory designs.

The reason lies in the lower yield of HBM chips compared to traditional memory chips. The complex stacking architecture of HBM involves multiple memory layers and Through-Silicon Via (TSV) technology for interconnecting layers, which increases manufacturing complexity. In the multi-layer stacking of HBM, if any of the HBM chips are defective, the entire stack will be discarded.

HBM, a type of DRAM primarily used in AI servers, is experiencing a surge in demand worldwide, led by NVIDIA. Moreover, according to a previous TrendForce press release, the three major original HBM manufacturers held market shares as follows in 2023: SK Hynix and Samsung were both around 46-49%, while Micron stood at roughly 4-6%.

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(Photo credit: SK Hynix)

On March 4th, Chinese assembly and testing company, JCET Group (JCET), announced its intention to acquire 80% equity of SanDisk Semiconductor Shanghai Co., Ltd. (SDSS), a subsidiary of Western Digital Corporation (WDC), for USD 624 million in cash. This strategic move aims to expand JCET’s market share in the storage.

The assembly and testing market competition is intensifying, especially with Moore’s Law slowing down in recent years. While advanced process technology still requires time, the demand for computing is skyrocketing.

As a result, advanced packaging is highly anticipated. Over the past two years, several testing and packaging giants have continuously enhanced their market competitiveness through mergers, expansion, and innovative technologies.

JCET Ventures into Storage with CNY 4.5 Billion Investment

According to the announcement, JCET has signed a “Equity Acquisition Agreement” with SANDISK CHINA LIMITED, the parent company of SANDISK CHINA LIMITED – SSDS.

Per the agreement, JCET Group intends to acquire 80% of the equity of SSDS held by the seller in cash. The transaction price, after full communication and negotiation between the parties, is approximately USD 624 million. After the completion of this transaction, JCET Group will hold 80% of the equity of SSDS, while SANDISK CHINA LIMITED will retain 20% ownership in SSDS.

According to the information available, SSDS was established in August 2006 and primarily engages in the research and development, packaging, and testing of advanced NAND Flash memory. Its product range includes iNAND flash modules, SD cards, MicroSD memory cards, etc., widely used in mobile communications, industrial IoT, automotive, smart home, consumer electronics, and other fields.

The selling party’s parent company, WDC, is a global leader in storage solutions. According to TrendForce’s data, in the third quarter of 2023, Western Digital held a market share of 16.9% in global NAND Flash revenue rankings, securing the third position worldwide.

Per the announcement, WDC has had a long-standing partnership with JCET since 2003, making it one of JCET’s key clients. JCET stated that following the completion of this transaction, the selling party (SANDISK CHINA LIMITED) and its parent company (Western Digital) will continue to be the primary or sole customers of SSDS for a certain period, ensuring a level of stability in its operational performance.

In its announcement of the acquisition of SSDS, JCET explicitly states that this decision stems from an in-depth analysis and forward-looking assessment of the global storage market.

As per the World Semiconductor Trade Statistics (WSTS), storage chips have emerged as the second-largest semiconductor sub-market, capturing approximately 28% of market share, trailing only behind logic chips. Looking ahead, it is projected that by 2024, the storage chip market will reach a staggering USD 130 billion in size.

Within this expansive market, NAND flash chips stand out, constituting approximately 40% of the global storage market. Moreover, it is projected to maintain a compound annual growth rate (CAGR) of 8% from 2021 to 2027. This indicates that the NAND flash chip market is not only vast but also possesses stable growth potential.

Intense Competition in the Semiconductor Packaging Market: Focus on Advanced Packaging

Major semiconductor packaging companies like ASE, Amkor Technology, Powertech, and Huatian Technology are continuously enhancing their competitive edge through expansions and acquisitions, driving rapid growth in the semiconductor packaging industry.

• ASE

Regarding ASE, it recently announced that its capital expenditure for this year is expected to increase by 40% to 50% compared to last year, with 65% allocated to packaging, especially for advanced packaging projects.

On February 22nd, ASE Group and semiconductor giant Infineon Technologies jointly announced the finalization of an agreement. ASE Group will invest EUR 62.589 million to acquire Infineon’s backend packaging facilities located in Cavite, Philippines, and Cheonan, South Korea.

In November 2022, ASE initiated construction on its fourth and fifth plants in Penang, Malaysia, with completion slated for 2025. Besides Malaysia, ASE continues its expansion efforts in Taiwan, including Kaohsiung, Zhongli, and Tanzi.

• Amkor

On January 16th, Amkor and semiconductor foundry Globalfoundries held a ribbon-cutting ceremony for the joint construction of the Amkor Porto plant in Portugal. Since February 2023, Globalfoundries has relocated 50 devices from its Dresden facility to Amkor’s new Porto plant.

The initial batch of client products has been certified using Globalfoundries’ equipment. Globalfoundries is transferring some of its 300mm production lines from Dresden to Amkor’s Porto facility, which is IATF16949 certified, to establish Europe’s first large-scale test and packaging plant.

• Powertech

In 2023, the packaging and testing firm, Powertech, expressed optimism about the future development of advanced packaging technologies. Powertech has outlined plans to resume significant capital expenditures in the latter half of 2024, ensuring sustained investments to maintain a competitive edge and prepare for long-term growth.

• Huatian Technology

In March 2023, Huatian Technology made significant strides by investing 2.858 billion yuan in its wholly-owned subsidiary, Huatian Technology (Jiangsu) Co., Ltd., for the construction of the “High-Density, High-Reliability Advanced Packaging Research and Industrialization” project.

Once completed, the project will enable an annual wafer-level integrated circuit packaging capacity of 840,000 pieces for Bumping, 480,000 pieces for WLCSP, and 26,000 pieces for ultra-high-density fan-out UHDFO. The construction period spans 5 years, from June 2023 to June 2028.

Currently, the packaging market’s competitive landscape extends beyond traditional OSATs, with major foundries and storage giants actively joining the fray. Technologies like TSMC’s SoIC, CoWoS, and InFO, Intel’s EMIB, Foveros, and Co-EMIB, as well as Samsung’s I-Cube (2.5D) and X-Cube (3D), are emerging and maturing.

The proliferation of various 2.5D and 3D packaging solutions indicates that competition in advanced packaging will only intensify, promising an exciting future ahead.

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(Photo credit: JCET Group)