With the flourishing development of technologies such as AI, cloud computing, big data analytics, and mobile computing, modern society has an increasingly high demand for computing power.

Moreover, with the advancement beyond 3 nanometers, wafer sizes have encountered scaling limitations and manufacturing costs have increased. Therefore, besides continuing to develop advanced processes, the semiconductor industry is also exploring other ways to maintain chip size while ensuring high efficiency.

The concept of “heterogeneous integration” has become a contemporary focus, leading to the transition of chips from single-layer to advanced packaging with multiple layers stacked together.

The term “CoWoS” can be broken down into the following definitions: “Cow” stands for “Chip-on-Wafer,” referring to the stacking of chips, while “WoS” stands for “Wafer-on-Substrate,” which involves stacking chips on a substrate.

Therefore, “CoWoS” collectively refers to stacking chips and packaging them onto a substrate. This approach reduces the space required for chips and offers benefits in reducing power consumption and costs.

Among these, CoWoS can be further divided into 2.5D horizontal stacking (most famously exemplified by TSMC’s CoWoS) and 3D vertical stacking versions. In these configurations, various processor and memory modules are stacked layer by layer to create chiplets. Because its primary application lies in advanced processes, it is also referred to as advanced packaging.

According to TrendForce’s data, it has provided insights into the heat of the AI chip market. In 2023, shipments of AI servers (including those equipped with GPU, FPGA, ASIC, etc.) reached nearly 1.2 million units, a 38.4% increase from 2022, accounting for nearly 9% of the overall server shipments.

Looking ahead to 2026, the proportion is expected to reach 15%, with a compound annual growth rate (CAGR) of AI server shipments from 2022 to 2026 reaching 22%.

Due to the advanced packaging requirements of AI chips, TSMC’s 2.5D advanced packaging CoWoS technology is currently the primary technology used for AI chips.

GPUs, in particular, utilize higher specifications of HBM, which require the integration of core dies using 2.5D advanced packaging technology. The initial stage of chip stacking in CoWoS packaging, known as Chip on Wafer (CoW), primarily undergoes manufacturing at the fab using a 65-nanometer process. Following this, through-silicon via (TSV) is carried out, and the finalized products are stacked and packaged onto the substrate, known as Wafer on Substrate (WoS).

As a result, the production capacity of CoWoS packaging technology has become a significant bottleneck in AI chip output over the past year, and it remains a key factor in whether AI chip demand can be met in 2024. Foreign analysts have previously pointed out that NVIDIA is currently the largest customer of TSMC’s 2.5D advanced packaging CoWoS technology.

This includes NVIDIA’s H100 GPU, which utilizes TSMC’s 4-nanometer advanced process, as well as the A100 GPU, which uses TSMC’s 7-nanometer process, both of which are packaged using CoWoS technology. As a result, NVIDIA’s chips account for 40% to 50% of TSMC’s CoWoS packaging capacity. This is also why the high demand for NVIDIA chips has led to tight capacity for TSMC’s CoWoS packaging.

TSMC’s Expansion Plans Expected to Ease Tight Supply Situation in 2024

During the earnings call held in July 2023, TSMC announced its plans to double the CoWoS capacity, indicating that the supply-demand imbalance in the market could be alleviated by the end of 2024.

Subsequently, in late July 2023, TSMC announced an investment of nearly NTD 90 billion (roughly USD 2.87 billion) to establish an advanced packaging fab in the Tongluo Science Park, with the construction expected to be completed by the end of 2026 and mass production scheduled for the second or third quarter of 2027.

In addition, during the earnings call on January 18, 2024, TSMC’s CFO, Wendell Huang, emphasized that TSMC would continue its expansion of advanced processes in 2024. Therefore, it is estimated that 10% of the total capital expenditure for the year will be allocated towards expanding capacity in advanced packaging, testing, photomasks, and other areas.

In fact, NVIDIA’s CFO, Colette Kress, stated during an investor conference that the key process of CoWoS advanced packaging has been developed and certified with other suppliers. Kress further anticipated that supply would gradually increase over the coming quarters.

Regarding this, J.P. Morgan, an investment firm, pointed out that the bottleneck in CoWoS capacity is primarily due to the supply-demand gap in the interposer. This is because the TSV process is complex, and expanding capacity requires more high-precision equipment. However, the long lead time for high-precision equipment, coupled with the need for regular cleaning and inspection of existing equipment, has resulted in supply shortages.

Apart from TSMC’s dominance in the CoWoS advanced packaging market, other Taiwanese companies such as UMC, ASE Technology Holding, and Powertek Technology are also gradually entering the CoWoS advanced packaging market.

Among them, UMC expressed during an investor conference in late July 2023 that it is accelerating the deployment of silicon interposer technology and capacity to meet customer needs in the 2.5D advanced packaging sector.

UMC Expands Interposer Capacity; ASE Pushes Forward with VIPack Advanced Packaging Platform

UMC emphasizes that it is the world’s first foundry to offer an open system solution for silicon interposer manufacturing. Through this open system collaboration (UMC+OSAT), UMC can provide a fully validated supply chain for rapid mass production implementation.

On the other hand, in terms of shipment volume, ASE Group currently holds approximately a 32% market share in the global Outsourced Semiconductor Assembly and Test (OSAT) industry and accounts for over 50% of the OSAT shipment volume in Taiwan. Its subsidiary, ASE Semiconductor, also notes the recent focus on CoWoS packaging technology. ASE Group has been strategically positioning itself in advanced packaging, working closely with TSMC as a key partner.

ASE underscores the significance of its VIPack advanced packaging platform, designed to provide vertical interconnect integration solutions. VIPack represents the next generation of 3D heterogeneous integration architecture.

Leveraging advanced redistribution layer (RDL) processes, embedded integration, and 2.5D/3D packaging technologies, VIPack enables customers to integrate multiple chips into a single package, unlocking unprecedented innovation in various applications.

Powertech Technology Seeks Collaboration with Foundries; Winbond Electronics Offers Heterogeneous Integration Packaging Technology

In addition, the OSAT player Powertech Technology is actively expanding its presence in advanced packaging for logic chips and AI applications.

The collaboration between Powertech and Winbond is expected to offer customers various options for CoWoS advanced packaging, indicating that CoWoS-related advanced packaging products could be available as early as the second half of 2024.

Winbond Electronics emphasizes that the collaboration project will involve Winbond Electronics providing CUBE (Customized Ultra-High Bandwidth Element) DRAM, as well as customized silicon interposers and integrated decoupling capacitors, among other advanced technologies. These will be complemented by Powertech Technology’s 2.5D and 3D packaging services.

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(Photo credit: TSMC)

Industry sources cited by the Liberty Times Net have pointed out that the Kumamoto plant holds significant importance for both Taiwan and Japan, as Japan is expected to look for attracting investments from TSMC, Intel, and Samsung to establish manufacturing facilities in the country.

TSMC stands out as essential due to its critical role as a key supplier to Apple, whose products are also utilized by the US military. Under geopolitical considerations, Apple needs to diversify its production beyond Taiwan and China. Therefore, it may hope TSMC can provide chip production in Japan soon and establish comprehensive advanced packaging services in the future. It seems inevitable that TSMC will eventually invest in setting up advanced packaging facilities in Japan.

Establishing Comprehensive Advanced Packaging Services

The TSMC Kumamoto plant commenced construction in April 2022 and was completed in just one year and eight months. While the construction of the US plant began in early 2021, setbacks in construction has led to the postponement of the production schedule from this year to the next.

Japan is also facing severe labor shortages, but the construction industry in Japan has made significant progress. It is highly industrialized, utilizing modular structures prefabricated in plants and then transported to construction sites for installation, thus reducing the need for on-site labor. In the construction of the Kumamoto plant, Japan’s construction firm, Kajima Corporation, was the general contractor.

German Construction Firm Sends Team to Learn from Japan

The German government actively subsidizes efforts to attract TSMC to invest in establishing  plants. In August last year, TSMC finalized partnerships with Bosch, Infineon, and NXP Semiconductors to form the European Semiconductor Manufacturing Company (ESMC) in Dresden, Germany.

According to a report from Liberty Times Net, construction is expected to begin in the second half of this year, with mass production slated to start by the end of 2027. It is also reported that Exyte, a German engineering services firm (formerly known as M+W), has recently sent a team to learn from the Kumamoto plant.

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(Photo credit: TSMC)

In a bid to enhance its foundry capabilities, Samsung is earnestly integrating hybrid bonding technology. According to industry sources, Applied Materials and Besi Semiconductor are establishing equipment for hybrid bonding at the Cheonan Campus, slated for use in next-generation packaging solutions like X-Cube and SAINT.

According to a report from South Korean media outlet The Elec, industry sources have indicated that Applied Materials and Besi Semiconductor are installing hybrid bonding equipment at Samsung’s Cheonan Campus, a key site for advanced packaging production. Officials from the South Korean industry also mentioned that a production line is currently under construction, with the equipment intended for non-memory packaging.

Compared to existing bonding methods, hybrid bonding enhances I/O and wiring lengths. Samsung’s latest investment is expected to strengthen its advanced packaging capabilities, introducing the X-Cube utilizing hybrid bonding technology.

Industry sources cited by the report have suggested that hybrid bonding could also be applied to Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform, which the company began introducing this year. The platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs. SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

TSMC, the leading semiconductor foundry, also offers hybrid bonding in its System on Integrated Chip (SoIC) for 3D packaging services, which is similarly provided by Applied Materials and Besi Semiconductor. Intel has also applied hybrid bonding technology in its 3D packaging technology, Foveros Direct, which was commercialized last year.

Reportedly, industry sources anticipate that Samsung’s investment in hybrid bonding facilities is poised to attract major clients such as NVIDIA and AMD. This is because the demand for hybrid bonding among fabless customers is steadily increasing.

(Photo credit: Samsung)

In the surge of AI advancements, a CoWoS expansion wave is rapidly underway, with TSMC showcasing ongoing ambitions in advanced packaging.

According to MoneyDJ, recent industry reports suggest that TSMC is revising upward its capacity plans for SoIC (System-on-Integrated-Chips). By the end of this year, monthly production capacity is expected to jump from around 2,000 units in late 2023 to 5,000-6,000 units, addressing robust demand in the future for AI and HPC.

TSMC’s SoIC represents an industry-first high-density 3D chip stacking technology. Through the Chip on Wafer (CoW) packaging technique, it enables heterogeneous integration of chips with different sizes, functions, and nodes. Production has commenced at its advanced backend Fab 6 in Zhunan.

Quoting industry sources, MoneyDJ reports that SoIC’s monthly capacity was initially set to expand to 3,000-4,000 units this year from 2,000 units at the end of last year. However, it is now revised upward to 5,000-6,000 units, with a goal to double the capacity by 2025.

CoWoS, a mature technology with 15 years of development, is estimated to reach a monthly capacity of 30,000-34,000 units by the end of this year. TSMC is banking on its globally dominant 3D stacking technology with SoIC. The debut of major customer AMD MI300 utilizing SoIC with CoWoS is seen as pivotal. If successful, AMD could dominate the AI server sector, making TSMC’s SoIC a significant achievement.

Furthermore, Apple, TSMC’s largest customer, is reportedly keenly interested in SoIC. It is said to adopt SoIC with Hybrid Molding technology, currently in small-scale trial production and expected to enter mass production in 2025-2026. The plan is to apply it in products like Mac and iPad, offering cost advantages over current solutions.

As for another major customer of TSMC’s advanced packaging, NVIDIA, although high-end products currently favor CoWoS packaging, the industry anticipates the future integration of SoIC technology.

(Image: TSMC)

Taiwanese Semiconductor testing and packaging giant ASE announced today that its subsidiary, ASE Semiconductor, will lease the plant in Nanzih, Kaohsiung, owned by Taiwan’s ASE Test Inc., to expand its packaging capacity.

In the announcement, ASE Holdings revealed that ASE Semiconductor would lease a plant in Nanzih District, Kaohsiung, from its subsidiary ASE Test Inc. The total floor area of the building is approximately 15,600 square meters, with an estimated total usage rights asset value of NTD 742 million (approximately USD 23.8 million).

ASE Holdings stated that the primary purpose of this move is to optimize the overall planning and efficient utilization of plant space within the group, as well as to expand ASE’s packaging capacity.

According to CNA’s report, industry sources believe that ASE’s primary objective with this expansion is to enhance its production capacity for advanced packaging of Artificial Intelligence (AI) chips, but it is not directly related to CoWoS packaging.

Market insiders point out that ASE Holdings has been collaborating with foundry on technologies related to advanced packaging interposers and has CoWoS solutions. The earliest expected time for mass production is by the end of this year or early next year.

Reportedly, according to data, ASE’s Kaohsiung plant contributes to approximately 20% of ASE Holding’s overall revenue. The plant primarily provides services such as packaging, wafer bumping and probing, materials, and final testing.

The Kaohsiung plant is also establishing several smart plants, focusing on high-end processes, including Fan-Out packaging, System-in-Package (SiP), wafer bumping, and FlipChip packaging. These technologies find applications in various fields, including automotive, medical, IoT, high-speed computing, artificial intelligence, and application processors.

ASE actively positions itself in various advanced packaging technologies. Notably, the Fan-Out Chip on Substrate with Bridge (FOCoS-Bridge) packaging technology integrates multiple Application-Specific Integrated Circuits (ASICs) and High Bandwidth Memory (HBM), targeting the customized AI chip advanced packaging market.

In addition, ASE Semiconductor has introduced a cross-platform integrated design tool that combines several advanced packaging technologies, addressing the demands of advanced packaging for AI chips.

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(Photo credit: ASE)