As TSMC’s earnings call approaches on April 18th, according to a source cited in a report from Commercial Times, it has predicted a downturn in the smartphone industry as it enters a slow season. However, TSMC is reportedly benefiting from AI demand, bolstering its operations through HPC (High-Performance Computing). Additionally, the increasing revenue share from the 3nm process is expected to contribute positively to performance in the second quarter.

TSMC has issued updates for three consecutive days, indicating that the overall recovery rate of its fabs has exceeded 80%. They reiterated their annual performance outlook from January’s earnings call, forecasting revenue growth in the low-to-mid twenties percentage range for the full year. Notably, in the fourth quarter of last year, the revenue share from high-performance computing matched that of smartphones, both reaching 43%, serving as dual engines for operational growth.

The same report, citing sources, indicates that TSMC’s advanced process technology and yield rates lead the industry, making it the primary foundry choice for most global customers.

Based on overall market share, TrendForce’s latest report reveals that in 2023, global foundry revenues hit US$117.47 billion, with TSMC capturing a dominant 60% share. This figure is expected to climb to around $131.65 billion in 2024, increasing TSMC’s share to 62%. It is also estimated in the report from Commercial Times that TSMC holds a market share of approximately 70-80% in 5nm technology, and this is expected to exceed 90% for 3nm, covering nearly all major players in the market.

TSMC has also emphasized that besides traditional smartphone applications, High-Performance Computing (HPC) is becoming an increasingly important application for their advanced processes. This means that even during the second quarter when demand for smartphone chips is typically lower, it will be supported by HPC demand.

The current major AI accelerators such as NVIDIA’s A100 and H100 GPUs, AMD’s Instinct MI250 and MI300, are all manufactured utilizing TSMC’s 7nm or 5nm nodes, highlighting TSMC’s critical position in the AI industry. Reportedly, as demand for AI-based Generative AI (AIGC) continues to rise, TSMC’s production volume is also expected to increase accordingly.

According to the same report citing sources, TSMC’s utilization rate for its 3nm production remains high and unaffected despite the impact of the recent earthquake on its facilities. TSMC has emphasized that key machines used for advanced processes, including all Extreme Ultraviolet (EUV), were undamaged.

However, in areas where the shaking was more severe, certain production lines are expected to require longer adjustments and calibration to restore automated production. TSMC is conducting a comprehensive review of the impact of this earthquake while maintaining close communication with its customers.

Furthermore, TSMC’s biggest challenge at the moment is how to catch up with customer expansion demands.

The most lacking capacity currently is in CoWoS production. Although TSMC maintains its stance of doubling capacity compared to 2023, market estimates cited in the report indicate that TSMC’s capacity is expected to increase from around 13,000 wafers to 30,000-35,000 wafers. This aligns with what founder Morris Chang described—AI chip demand in the future will no longer be in the tens or hundreds of thousands of wafers but will require the capacity of 3, 5, or even 10 fabs.

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(Photo credit: TSMC)

The semiconductor industry enters the era of integration. Various foundries are focusing on advanced packaging technologies, but the terminology surrounding advanced packaging can be daunting. This article aims to explain these terms in the simplest way possible.

According to a report from TechNews, currently, there are two main trends in advanced packaging: heterogeneous integration and chiplets.

In fact, the concept of “heterogeneous integration” has been developing for many years and is not exclusive to advanced packaging. It is not only used for the integration of heterogeneous chiplets but also for integrating other non-chip active/passive components into a single package, which is the technology commonly used in traditional Outsourced Semiconductor Assembly and Test Services(OSATs).

• Heterogeneous Integration = Big Building Blocks? Advanced Packaging = Small Building Blocks? 

In the simplest terms, “heterogeneous integration” can be likened to building with large building blocks, while “advanced packaging” is akin to assembling with small building blocks. Some manufacturers, like traditional Outsourced Semiconductor Assembly and Test Services(OSATs), excel in stacking large blocks, such as logic circuits, radio frequency circuits, MEMS (Micro-Electro-Mechanical Systems), or sensors, onto a IC substrate. The stacking of these different large blocks represents the concept of heterogeneous integration.

On the other hand, some blocks are too small to stack effectively, requiring assistance from advanced packaging, typically provided by semiconductor foundries.

Advanced packaging also encompasses 2.5D packaging and 3D packaging. Using the metaphor of building blocks, the former involves horizontally stacking small building blocks on a interposer, while the latter involves vertically stacking small building blocks with interconnection facilitated through Through-Silicon Vias (TSVs), which are ultra-small building blocks.

It’s important to emphasize that stacking blocks is a conceptual representation, and the distinction between large and small blocks is relative. The analogy above refers to heterogeneous integration in traditional packaging, and heterogeneous integration in advanced packaging follows a similar concept, but with even smaller building blocks.

• SoC / SiP / Heterogeneous Integration / Chiplet

With this concept in mind, let’s discuss the applications of heterogeneous integration in advanced packaging:

Among the various packaging types, SoC (System On Chip) involves integrating different chips such as processors and memory, with different functions, redesigned and fabricated using the “same process,” integrated onto a single chip, resulting in a final product with only one chip.

On the other hand, SiP (System in Package) involves connecting multiple chips with “different processes” through “heterogeneous integration” technology, integrated within the same packaging module. Therefore, the final product will be a system with many chips on it, resembling the stacking of different-sized building blocks mentioned earlier.

Therefore, heterogeneous integration refers to integrating different and separately manufactured components (heterogeneous) into higher-level assemblies. These components include blocks of different sizes, such as MEMS devices, passive components, logic chips, and more.

However, at a certain point, for the sake of process development, researchers found that separating components at the right time might facilitate miniaturization. Hence, chiplet was born.

• Is Chiplet the Fusion of Heterogeneous Integration and Advanced Processes?

As demands for ICs become increasingly complex, the size of SoC chips continues to grow. However, cramming too many components onto a limited substrate poses significant challenges, including heightened process complexity and reduced yield.

Hence, the concept of chiplets emerged, advocating for the segmentation of SoC functionalities, such as data storage, computation, signal processing, and data flow management, into smaller individual chips. These chiplets are then integrated through packaging to form a interconnected network.

It’s worth noting that Chiplets are essentially chips, whereas SiP refers to the packaging format. Chiplet architecture enable the reduction of individual chip sizes, simplify circuit design, overcome manufacturing difficulties and yield issues, and offer greater design flexibility.

• Advanced Packaging Technologies in Foundries

Currently, advanced packaging can be broadly categorized into three main types: Wafer-Level Packaging (WLP), 2.5D Packaging, and 3D Packaging. Traditional packaging involves cutting wafers into chips before packaging, while advanced packaging entails packaging the silicon wafer before cutting, requiring subsequent stacking processes in fabs. Therefore, the technology is primarily the responsibility of fabs.

Traditional packaging involves cutting wafers into chips before packaging. Advanced packaging, starting from wafer-level packaging, involves packaging silicon wafers before cutting, and subsequent stacking requires wafer fabrication processes.

Therefore, this article will delve into advanced packaging technologies offered by the three major foundries, with a focus on 2.5D and 3D packaging.

• 2.5DIC / 3DIC Packaging

To further explain using building blocks, the difference between 2.5D and 3DIC packaging lies in the “stacking method.”

In 2.5D packaging, processors, memory, or other chips are stacked horizontally on a silicon interposer using a flip-chip method, with micro bumps connecting different chip’s electronic signals. Through silicon vias (TSVs) in the interposer link to the metal bumps below, then packaged onto the IC substrate, creating tighter interconnections between the chips and the substrate.

In a side view, although the chips are stacked, the essence remains horizontal packaging, with the chips positioned closer together and allowing for smaller chip sizes. Additionally, this is a form of “heterogeneous integration” technology.

3D packaging involves stacking multiple chips (face down) together, directly using through-silicon vias to stack them vertically, linking the electronic signals of different chips above and below, achieving true vertical packaging. Currently, more and more CPUs, GPUs, and memories are starting to adopt 3D packaging technology.

• Hybrid Bonding

Hybrid bonding is one of the die bonding techniques used in advanced chip packaging processes. One of the commercially available technologies in this domain is the “Cu-Cu hybrid bonding.”

In traditional wafer bonding processes, there are interfaces between copper and dielectric materials. With “Cu-Cu hybrid bonding,” metal contacts are embedded within the dielectric material. Through a thermal treatment process, these two materials are bonded together, utilizing the atomic diffusion of copper metal in its solid-state to achieve the bond. This approach addresses challenges encountered in previous flip-chip bonding process.

Compared to flip-chip bonding, hybrid bonding offers several advantages. It allows for achieving ultra-high I/O counts and longer interconnect lengths. By using dielectric material for bonding instead of bottom fillers, the cost of filling is eliminated.

Additionally, hybrid bonding results in minimal thickness compared to chip-on-wafer bonding. This is particularly beneficial for future developments in 3D packaging, where stacking multiple layers of chips is required, as hybrid bonding can significantly reduce the overall thickness.

• Advanced Packaging Moves Towards the Era of Heterogeneous Integration

As the semiconductor industry enters the “post-Moore’s Law era,” the development focus of advanced packaging is gradually shifting from 2D planar structures to 3D stacking and from single-chip designs to multi-chip configurations. Therefore, “heterogeneous integration” will play a crucial role in future advanced packaging.

Currently, prominent companies such as TSMC, Samsung, and Intel are intensifying their research and development efforts and capacity expansions in this field, introducing their innovative packaging solutions.

With ongoing technological advancements and innovations, advanced packaging and heterogeneous integration will play increasingly vital roles in propelling the semiconductor industry towards greater heights, meeting the complex and diverse demands of future electronic devices.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: Intel)

Fueled by the advancement in TSMC’s N3 process technology, the average selling price (ASP) of TSMC’s 12-inch wafers increased to USD 6,611 in the fourth quarter of 2023, registering a year-on-year growth of 22% despite the subdued semiconductor market.

According to a report by TechNews, Bernstein Research has indicated that the current growth in most semiconductor industries stems from the increase in pricing rather than a rise in chip shipment volumes.

As per a report by Tom’s Hardware, the wafer shipment volume of TSMC serves as evidence in many aspects. In the fourth quarter of 2023, TSMC’s shipment of 12-inch wafers was 2.957 million units, lower than the 3.702 million units in the fourth quarter of 2022. This marks the first time since 2020 that TSMC’s 12-inch wafer shipments have fallen below 3 million units. However, the revenue showed only a marginal decline.

Despite a significant 20.1% decrease in the fourth-quarter shipment volume of TSMC’s 12-inch wafers compared to the previous year, the revenue for the quarter reached USD 19.62 billion, only a 1.5% decrease from USD 19.93 billion in the fourth quarter of 2022.

Meanwhile, the average price of TSMC’s processed 12-inch wafers in the fourth quarter of 2023 reached USD 6,611 per unit, surpassing the USD 5,384 per unit in the fourth quarter of 2022. This is attributed to the increased shipment volume of wafers at the N3 process to customers, including Apple.

The report further cites sources indicating that TSMC may charge up to USD 20,000 per wafer manufactured using its N3 process. Although this figure may not be entirely accurate as TSMC’s pricing depends on various factors, the key point is that TSMC’s fees for the N3 process are higher compared to the N4/N5 or N6/N7 process.

Therefore, it can be argued that TSMC’s increase in manufacturing prices for process nodes has played a significant role in driving almost all growth in the semiconductor industry in recent years.

In essence, as time progresses, new process nodes will become increasingly expensive. The total chip shipments from 2019 to 2023 have actually decreased, but the ASP has significantly increased.

In particular, TSMC’s wafer revenue for the fourth quarter of 2023 was notably influenced by its N3 process, contributing 15%, while the N5 and N7 process contributed 39% and 17%, respectively.

This breakdown signifies that the N3 process node generated USD 2.943 billion in revenue for TSMC, the N5 process contributed USD 6.867 billion, and the N7 process brought in USD 3.3354 billion.

Overall, TSMC’s advanced process (N7, N5, N3) accounted for 67% of its total wafer revenue. Among these, revenues from System-on-Chip (SoC) used in smartphones and high-performance computing applications each constituted 43%, automotive chip revenue made up 5%, and IoT chip revenue contributed 5%.

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• [News] TSMC’s N3P to Enter Mass Production in the Second Half of Next Year, Rumored Inclusion of Tesla in Customer List

(Photo credit: TSMC)

Despite the uncertainties in the semiconductor market, there is still an intense global competition in the development of advanced semiconductor manufacturing processes. TSMC as one of the key players in the foundry industry is actively advancing its next-generation 2nm process. According to market rumors, the schedule for the first tool-in at Hsinchu Baoshan Fab and Kaohsiung Fab has been established, along with a finalized production capacity plan.

CNA has reported that TSMC’s 2nm process will be deployed in the Phase 2 Expansion Area of the Baoshan Site at the Hsinchu Science Park. The first tool-in is scheduled for April 2024. Industry sources have revealed that the initial production capacity for this process will be around 30,000 wafers per month, with mass production planned for the following year.

In addition, TSMC’s fab in Kaohsiung has notified equipment suppliers that this facility is set to begin in the third quarter of 2025. According to MoneyDJ, the pilot run is planned for the end of the same year, with the aim of achieving mass production in 2026. The Kaohsiung fab will adopt the N2P process, which is an enhanced version of the 2nm process with the backside power rail technology. The initial monthly production capacity is also expected to be around 30,000 wafers.

According to previous disclosures made by TSMC during financial calls, the company has developed a backside power rail solution for the N2 process, which is particularly suitable for high-performance computing (HPC) applications. This innovative technology is expected to boost speed by 10% to 12% and increase logic density by 10% to 15%. TSMC plans to introduce the backside power rail solution to customers in the latter half of 2025, with mass production scheduled for 2026. This timetable aligns with recent rumor circulating in the supply chain.

In addition to the latest progress on the N2P process, TSMC made an official announcement at the IEEE International Electron Devices Meeting (IEDM) on December 12th. Specifically, the company revealed its plans to introduce a 1.4nm process as the successor to the 2nm process. As reported by Tom’s Hardware, this new process, named A14, continues the naming convention from the 2nm process (A20). Production using the A14 process is anticipated to take place between 2027 and 2028.

(Image: TSMC)

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• [News] TSMC May Reduce Next Year’s Capital Expenditure, Affecting Orders for Equipment & Testing-Related Companies

Market speculations rumored that TSMC might cut its capital expenditure for next year to USD 28-30 billion. This potential reduction, ranging from 6.3% to 12.5% compared to this year, is attributed to the shared use of certain process equipment and the utilization of deferred budgets from the current year. If realized, this would mark the lowest capital expenditure point in nearly four years. Additionally, it could impact the order volumes for equipment & testing-related companies, influencing the overall order dynamics in the supply chain for the upcoming year, reported by UDN News.

Responding to the speculations about a decrease in next year’s capital expenditure, TSMC stated on the December 4th that regarding next year’s capital expenditure will be officially disclosed during the January 2024 conference. Despite the potential moderation in capital expenditure, industry observers anticipate continued growth in R&D investment, particularly in advanced process technology.

Industry sources suggest that TSMC’s R&D investment in advanced process technology will persist in its growth trajectory for the next year. Notably, approximately 80% of the equipment for the 3nm advanced process can be shared with the 5nm and 7nm processes. The focus of next year’s capital expenditure is expected to be on investments in the 3nm and below advanced processes and mask technology.

Meanwhile, mature processes will bring a rise in the share of specialty processes and equipment modifications for advanced packaging.

During 2023Q3 earnings call in October, TSMC set a cautious tone, citing uncertainties in the short-term market. The company maintained this year’s capital expenditure at nearly USD 32 billion, adopting a prudent approach to investment.

On the other hand, ASML, the global leader in semiconductor lithography technology, recently released its financial report. The forecast indicates that 2024 will be a transitional year, with expected revenue similar to that of 2023. This cautious outlook aligns with the semiconductor industry’s current phase of experiencing the bottom of the cycle.

(Image: TSMC)