NVIDIA’s next-generation Blackwell architecture AI superchip is about to ship. According to a report from Commercial Times, on July 29 during the SIGGRAPH conference in Denver, USA, NVIDIA announced a series of software updates and revealed that samples of the new AI chip architecture Blackwell have been distributed, sparking optimism about the company’s continued record-breaking performance.

Industry sources cited by the report have indicated that the Blackwell series is regarded by Jensen Huang as the most successful product in history. It is expected to drive a new wave of AI server data center construction by cloud service providers (CSPs).

The report notes further that in addition to TSMC’s 4nm process being in high demand, the increasing penetration of water cooling technology, which is projected to reach up to 10%, is likely to benefit Cooling Distribution Unit suppliers such as Vertiv, as well as companies like Asia Vital Components, AURAS Technology, Delta Electronics, and Cool IT.

Furthermore, the new AI superchip is expected to start shipping to clients in the fourth quarter, with full-scale production set for 2025. Assembly plants will also benefit, including Wistron, Foxconn (through its subsidiary Ingrasys), which are involved in front-end manufacturing of substrates, computing boards, and switch boards.

Companies such as Wiwynn, Quanta (Quanta Cloud Technology), Inventec, GIGABYTE, ASUS, and ASRock are also expected to see increased orders for their rack-mounted systems. Among these, Quanta, Wiwynn, and Inventec have indicated that their related products are expected to start shipping in the fourth quarter, with further increases in volume anticipated in the first half of next year.

The NVIDIA Blackwell platform is set to become the main solution for NVIDIA’s high-end GPUs. TrendForce estimates that GB200 NVL36 shipments are expected to reach 60,000 units in 2025, with Blackwell GPU usage between 2.1 to 2.2 million units, making Blackwell the mainstream platform and accounting for over 80% of NVIDIA’s high-end GPUs.

TrendForce observes that the GB200 NVL36 architecture will initially utilize a combination of air and liquid cooling solutions, while the NVL72, due to higher cooling demands, will primarily employ liquid cooling.

Read more

• [News] NVIDIA Reportedly Developing Tailored Version of the Blackwell Series for Chinese Market
• [News] NVIDIA CEO Jensen Huang Estimates Blackwell Chip Price Around USD 30,000 to USD 40,000

(Photo credit: NVIDIA)

On July 30, 2024, SK hynix announced the launch of next-generation memory product, GDDR7, with the world’s highest performance.

SK hynix explained that GDDR is characterized by the performance specifically designed for graphic processing and high-speed property, which has gaining an increasingly more traction from global AI application customers. In response to this trend, the company completed the development of the latest GDDR7 specifications in March this year, which was now officially launched and will achieve mass production in the third quarter of this year.

SK hynix’s GDDR7 features an operating speed of up to 32Gbps (32 gigabytes per second), which represents an increase of more than 60% compared to the previous generation, and can stand at 40Gbps depending on the usage environment. Built on the latest graphics card, it can support data processing speed of over 1.5TB per second, equivalent to processing 300 FHD (5GB) movies in one second.

In addition to providing faster speeds, GDDR7 boasts an energy efficiency 50% higher than the previous generation. To address chip heating issue caused by ultra-high-speed data processing, SK hynix adopted new packaging technology in the development of this product.

SK hynix’s technical team maintained the product size while increasing the heat-dissipating layers in the packaging substrate from four to six and used highly thermally conductive epoxy molding compound (EMC) in the packaging materials. As a result, the technical team successfully reduced the thermal resistance of the product by 74% compared to the previous generation.

Lee Sang-kwon, Vice President of SK hynix DRAM PP&E, said that SK hynix’s GDDR7 has achieved the highest performance of existing memory chips with excellent speed and energy efficiency, and its applications will expand from high-performance 3D graphics to AI, HPC, and autonomous driving.

Through this product, the company will further strengthen its high-end memory product line while developing into the most trustworthy AI memory solution company for customers.

Read more

• [News] GDDR7 Emerging as a New Driver for Memory Industry
• [News] SK hynix to Kick off Mass Production for GDDR7 in Q4 2024

(Photo credit: SK hynix)

According to a report from UDN, China’s largest semiconductor packaging and testing company, JCET, has completed the planning and verification work for the first phase of the “JCET Microelectronics Wafer-level Microsystems Integration High-end Manufacturing Project.”

The project will soon be completed and put into production. Once operational, it will have an annual production capacity of 6 billion high-end advanced packaging chips, providing one-stop services from collaborative packaging design to chip production for 5G, artificial intelligence, and other applications.

As per WeChat account DRAMeXchange citing sources, the project is a major industrial initiative in Jiangsu Province, China, with a total investment of CNY 10 billion. Upon completion of the first phase, the project will have an annual production capacity of 6 billion high-end advanced packaging chips.

The project will focus on leading-edge high-performance packaging technologies, such as 2.5D/3D high-density wafer-level packaging. JCET Microelectronics commenced construction of its new plant in the eastern part of Jiangyin City on July 29, 2022, with the project expected to be completed and put into production between June and July 2024.

At the groundbreaking ceremony in 2022, JCET CEO Zheng Li stated that this project will represent the highest production technology level and largest single-investment smart manufacturing project in China’s integrated circuit packaging and testing and chip manufacturing industry. Thus, it will support end applications such as 5G, artificial intelligence, the Internet of Things, and automotive electronics, covering key strategic customers worldwide.

This project, per Li, will further enhance JCET’s global market competitiveness in the chip manufacturing sector, aiming to achieve a higher industrial position in the global integrated circuit industry.

Read more

• [News] China“Big Fund” Phase II Invested in a Fab and a Silicon Material Fab
• [News] Chinese Packaging Giant JCET Group Invests CNY 4.5 Billion to Enter Storage Market

(Photo credit: JCET Group)

Amid the wave of AI applications, the demand for high-performance memory continues to mushroom, with DRAM, represented by HBM, gaining significant traction. Meanwhile, to further meet market demand, memory manufacturers are  poised to embrace a new round of DRAM technological “revolution.”

• 4F Square DRAM being Developed Smoothly

According to a report from Korean media outlet Chosun Biz, Samsung Electronics Vice President Changsik Yoo recently announced that Samsung’s next-generation DRAM technology is progressing well. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also proceeding smoothly, with the initial sample of 4F Square DRAM set to be developed by 2025.

Industry sources cited by WeChat account DRAMeXchange indicate that the early DRAM cell structure was 8F Square, while currently commercialized DRAM mainly uses 6F Square. Compared to these two technologies, 4F Square employs a vertical channel transistor (VCT) structure, which can reduce the chip surface area by 30%.

As the cell area decreases, DRAM density and performance increase. Therefore, driven by applications like AI, 4F Square technology is gradually sought after by major storage manufacturers.

Previously, Samsung stated that many companies are working to transition their technology to 4F Square VCT DRAM, although some challenges need to be overcome, including the development of new materials like oxide channel materials and ferroelectrics.

Industry sources believe that the initial sample of Samsung’s 4F Square DRAM in 2025 might be for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will come out between 2027 and 2028.

Furthermore, earlier media reports mentioned that Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is a next-generation packaging technology referring to vertically stack chips to increase cell density and thus improve performance, which will also exert an influence on the development of HBM4 and 3D DRAM.

• HBM4 on the Horizon

In the era of AI, HBM, particularly HBM3e, has thrived in the memory market, prompting fierce competition among the three major DRAM manufacturers. A new race is now underway, primarily focusing on the next-generation HBM4 technology.

In April of this year, SK Hynix announced a partnership with TSMC to jointly develop HBM4. It is reported that the two companies will first work on performance improvements for the base die fitted at the bottom layer within the HBM package. To focus on the development of next-generation HBM4 technology, Samsung has established a new “HBM Development Team.”

In July, Choi Jang-seok, head of the New Business Planning Group in Samsung Electronics’ memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, expected to go into production next year. Recently, Samsung reportedly plans to use a 4nm advanced process to produce HBM4 logic die. Micron, on the other hand, plans to introduce HBM4 between 2025 and 2027 and transition to HBM4E by 2028.

Aside from manufacturing processes, DRAM manufacturers are actively exploring hybrid bonding technology for future HBM products. Compared to existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed, better matching the high bandwidth requirements of AI computing.

In April of this year, Korean media outlet The Elec reported that Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, with the memory sample functioning normally. This 16-layer stacked hybrid bonding technology will be used to produce HBM4 at scale in the future. SK Hynix plans to adopt hybrid bonding in its HBM production by 2026. Micron is also developing HBM4 and is considering related technologies, including hybrid bonding, which are all under research at present.

• The Development of 3D DRAM Picks up Steam

3D DRAM (Three-dimensional dynamic random-access memory) represents a new DRAM technology with a novel memory cell structure. Unlike traditional DRAM, which places memory cells horizontally, 3D DRAM vertically stacks memory cells, greatly increasing storage capacity per unit area and improving efficiency. This makes it a key development for the next generation of DRAM.

In the memory market, 3D NAND Flash has already achieved commercial application, while 3D DRAM technology is still under research and development. However, as AI, big data, and other applications enjoy burgeoning growth, the demand for high-capacity, high-performance memory will surge, and 3D DRAM is expected to become a mainstream product in the memory market.

HBM technology has paved the way for the 3D evolution of DRAM, enabling DRAM to transition from traditional 2D to 3D. However, current HBM cannot be considered as true 3D DRAM technology. Samsung’s 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in 3D DRAM.

Samsung plans to achieve the commercialization of 3D DRAM by 2030. In 2024, Samsung showcased two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, then upgraded to stacked DRAM by stacking multiple VCTs together to continuously improve DRAM capacity and performance.

Samsung states that stacked DRAM can fully utilize the Z-axis space, accommodating more memory cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung noted that it, along with other companies, successfully manufactured 16-layer 3D DRAM, but emphasized that it is not ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and BSPDN (Backside Power Delivery Network) technology is also considered.

Regarding Micron, industry sources cited by DRAMeXchange reveal that Micron has filed for a 3D DRAM patent application different from Samsung’s, aiming to alter the shape of transistors and capacitors without placing cells.

BusinessKorea reported in June that SK Hynix achieved a manufacturing yield of 56.1% for its 5-layer stacked 3D DRAM. This means that out of around 1000 3D DRAMs produced on a single test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM demonstrated characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix disclosed specific numbers and features of its 3D DRAM development.

Besides, American company NEO Semiconductor is also engaging in the development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world’s first 3D DRAM prototype: 3D X-DRAM. This technology resembles 3D NAND Flash, namely increasing memory capacity by stacking layers, offering high yield, low cost, and remarkably high density.

NEO Semiconductor plans to launch the first generation of 3D X-DRAM in 2025, featuring a 230-layer stack and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.

Read more

• [News] Korean Semiconductor Exports Hit a New High, with Memory Shipment up by 88.7%
• [News] Korean Advanced Packaging Industry’s Rise Delayed by TSMC and ASE Expansion

(Photo credit: SK Hynix)

As TSMC and other major chip manufacturers compete for AI business opportunities, chip production capacity is unable to keep up with demand. Industry sources cited in a report from NIKKEI claimed that the slow expansion of high-end chip production capacity is due to different packaging and testing technologies used by various companies and calls for the industry to standardize as soon as possible.

Jim Hamajima, President of the Japan office of the Semiconductor Equipment and Materials International (SEMI), recently stated in an interview with NIKKEI that leading chip manufacturers like Intel and TSMC should adopt international standards for back-end processes to effectively and quickly increase production capacity.

Hamajima further noted that each company is trying to apply unique solutions in back-end processes, with TSMC and Intel using different technical standards, which leads to inefficiencies.

Semiconductor manufacturing is divided into two major parts: front-end and back-end processes. While the photolithography technology used in front-end processes widely adopts international standards set by SEMI, packaging and testing in back-end processes vary among manufacturers. For example, TSMC uses CoWoS technology for advanced packaging, while Samsung Electronics uses I-Cube technology.

In recent years, chip manufacturers have actively invested in the development of advanced packaging technologies, primarily because front-end processes face technical bottlenecks, making back-end processes the key to gaining a competitive edge.

Hamajima believes that the current state of back-end processes in the semiconductor industry is “Balkanized,” with each company adhering to its own technologies, leading to a fragmented industry. He warns that this issue will start to impact profit margins as more powerful chips are produced in the future.

Hamajima stated that if semiconductor manufacturers adopt standardized automated production technologies and material specifications, it will be easier to acquire manufacturing equipment and upstream material supplies when expanding production capacity.

Hamajima is a director of a recently launched consortium led by Intel and 14 Japanese companies to jointly develop automated systems for back-end processes. The collaborating companies include Japanese companies such as Omron, Yamaha Motor, Resonac, and Shin-Etsu Polymer, a subsidiary of Shin-Etsu Chemical Industry.

Hamajima noted that Japan, with its numerous automation equipment and semiconductor material suppliers, is an ideal location to test international standards for back-end processes.

He also acknowledged that currently, Intel is the only multinational chip manufacturer in the alliance, which might lead to the development of technical standards that favor Intel. However, he emphasized that the alliance welcomes other chip manufacturers to join, and the research outcomes will serve as a reference for future industry standard-setting.

Read more

• [News] Intel Reportedly Collaborates with 14 Japanese Companies to Develop Semiconductor Backend Process Technology
• [News] HBM Boom May Lead to DRAM Shortages in the Second Half of the Year

(Photo credit: TSMC)