As Samsung eagerly accelerates its pace on the HBM3e certification with NVIDIA, SK hynix, the current HBM market leader, is reportedly planning another move to strengthen its relationship with the AI giant. According to a report by Korean media Money Today, SK hynix is teaming up with Amkor Technology to target the silicon interposer market, eyeing to become a supplier for NVIDIA.

Citing sources from the semiconductor industry, the report notes that SK hynix has discussed with Amkor, the world’s second-largest OSAT (Outsourced Semiconductor Assembly and Test) company, about sending interposer samples. The process involves SK hynix sending its HBM and interposers to Amkor, which then combines them with GPUs from customers like NVIDIA to assemble AI accelerators.

A silicon interposer is a substrate on which GPUs and HBM are arranged and connected with the 2.5D/3D packaging. According to the report, drawing circuits on silicon to connect chips allows for more precise circuitry compared to using PCBs (Printed Circuit Boards) in traditional 2D packaging, which makes silicon interposers essential for packaging AI accelerators like NVIDIA’s A100 and H100.

Regarding the rumor, citing a SK hynix representative, the report states that the discussion is still in the early stages, while the company is conducting various reviews to provide interposers that meet customer demands.

It is worth noting that the entry barrier for silicon interposers seems to be high, as only a few semiconductor giants, including TSMC, UMC and Samsung, can supply silicon interposers with their own packaging technologies, such as TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) technology and Samsung’s I-Cube.

As Samsung is currently providing NVIDIA with its silicon interposers and I-Cube packaging services, SK hynix tries to further expand its leadership in HBM by entering the silicon interposer sector, the report notes, which may also alleviate the supply shortage for HBM and interposers as NVIDIA’s AI accelerators are in high demand.

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(Photo credit: SK hynix)

To enhance the supply chain capabilities in Europe and strengthen outsourced backend manufacturing operations in the region, major automotive and power semiconductor manufacturer Infineon announced an expanded partnership with semiconductor packaging and testing services provider Amkor Techology. According to the official press release of Infineon, the two companies will establish a new packaging and testing center in Porto, Portugal, with operations expected to commence in the first half of 2025.

Through this agreement, Infineon and Amkor will further strengthen their partnership and expand the semiconductor assembly and testing business model while enhancing the resilience of the European semiconductor supply chain.

Amkor’s facility in Porto, Portugal specializes in semiconductor packaging, assembly, and testing. As part of the reported expansion, cleanroom production lines will be established. Infineon is expected to provide product design and development expertise, as Infineon already operates a large service center in Porto with over 600 employees.

Infineon noted that the establishment of this production center will allow for further expansion of business in Portugal and reinforce the importance of Europe as a semiconductor manufacturing base. This initiative is anticipated to enhance regional manufacturing flexibility and supply security for customers.

On another front, Infineon recently announced a memorandum of understanding with HD Korea Shipbuilding & Offshore Engineering (HD KSOE), a company dedicated to developing environmentally friendly and low-carbon shipping technologies using electricity and hydrogen power. Together, they will leverage power semiconductor technology to jointly develop emerging marine engines and electrification of mechanical systems, accelerating the realization of low-carbon shipping.

In this collaboration, Infineon will provide technical support and guidance to HD KSOE in terms of power semiconductor modules and system solutions. Infineon will also share information on semiconductor trends relevant to maritime applications. The goal of HD KSOE is to enhance the reliability and performance of ship propulsion and drive technologies through this partnership, promoting environmental sustainability through maritime electrification initiatives.

(Photo credit: Infineon)

The surge in demand for advanced packaging is being primarily propelled by artificial intelligence (AI) chips. According to industry sources cited by CNA, TSMC’s CoWoS production capacity is set to double this year, yet demand continues to outstrip supply. In response, NVIDIA has enlisted the help of packaging and testing facilities to augment its advanced packaging capabilities.

In addition, to address the imbalance between supply and demand for advanced packaging due to AI, semiconductor backend specialty assembly and testing (OSAT) companies such as ASE Technology Holding (ASE), Powertech Technology, and KYEC have expanded their capital expenditures this year to enhance their advanced packaging capabilities, aligning with the needs of their customers.

AI and high-performance computing (HPC) chips are driving the demand for CoWoS advanced packaging. As per sources interviewed by CNA, from July to the end of last year, TSMC actively adjusted its CoWoS advanced packaging production capacity, gradually expanding and stabilizing mass production.

The source further indicates that in December of last year, TSMC’s CoWoS monthly production capacity increased to 14,000 to 15,000. It is estimated that by the fourth quarter of this year, TSMC’s CoWoS monthly production capacity will significantly expand to 33,000 to 35,000.

Per an earlier report from Commercial Times, TSMC has been outsourcing part of its CoWoS operations for some time, mainly targeting small-volume, high-performance chips. TSMC maintains in-house production of the CoW, while the back-end WoS is handed over to test and assembly houses to improve production efficiency and flexibility. 

However, the demand for advanced packaging capacity for AI chips still outstrips supply. Sources cited by CNA also reveal that NVIDIA has sought assistance from packaging and testing subcontractors outside of TSMC to augment their advanced packaging capabilities.

Amkor, among others, began gradually providing capacity support from the fourth quarter of last year, while SPIL, a subsidiary of ASE, is slated to commence supply in the first quarter of this year.

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(Photo credit: TSMC)

TSMC operates at full capacity, AMD aims for AI chips reportedly seeks CoWoS-like supply chain.

In 2023, NVIDIA led the global AI chip development, and in 2024, the global demand for AI chips is expected to continue to surge due to the expansion of end-user applications such as PCs and mobile phones.

Meanwhile, AMD has not stopped in AI chip development either, with the expected MI300 products poised to heat up the global AI business opportunities. However, the key to supply lies in advanced packaging, and AMD will seek outsourced semiconductor assembly and test (OSAT) service providers to offer support similar to CoWoS.

According to Taiwan’s Commercial Times, TSMC’s CoWoS capacity has long been fully loaded, and even if it expands production this year, it will mainly be reserved for NVIDIA. Market sources pointed out that TSMC will continue to increase CoWoS capacity to support AMD’s demand, but it takes six to nine months to establish a new production line. Therefore, it is expected that AMD will seek cooperation with other companies with CoWoS-like packaging capabilities. ASE, Amkor, Powertech, and KYEC are the first batch of potential partners.

TSMC has been outsourcing part of its CoWoS operations for some time, mainly targeting small-volume, high-performance chips. TSMC maintains in-house production of the CoW, while the back-end WoS is handed over to test and assembly houses to improve production efficiency and flexibility. This model will continue in the future 3D IC generation.

ASE and Amkor both received WoS orders last year. ASE has strengthened the development of advanced packaging technology and has a complete solution for the entire CoWoS process. ASE previously stated that it sees the strong potential of AI and expects related revenue to double in 2024.

According to reports citing market sources, the monthly production capacity of the ASE Group’s 2.5D packaging is about 2,000 to 2,500 pieces. Some experts believe that test and assembly houses will maintain the business model of TSMC or UMC providing the interposer. Therefore, in 2024, a significant increase in CoWoS production capacity is expected.

KYEC is responsible for testing Nvidia AI chips and is expected to benefit from AMD’s search for CoWoS-like capacity. Nvidia is currently KYEC’s second-largest customer.

KYEC’s testing of Nvidia A100 and H100 chips is mainly in the final test (FT), with a market share of up to 70%. KYEC provides comprehensive IC burn-in testing, has self-developed burn-in equipment, and has been in the industry for more than a decade, accumulating many patents and technologies.

AMD stated at the end of 2023 that AI chip revenue could reach US$2 billion in 2024, excluding other HPC chips. AMD pointed out that the annual compound growth rate of the AI chip market in the next four years will reach 70%, and it is estimated that it will reach US$400 billion in 2027.

(Image: AMD)

As reported earlier, the global provider of outsourced semiconductor packaging and test services, Amkor, has been set to establish its presence in Arizona, USA, providing advanced packaging services for Apple chips manufactured by TSMC.

According to reports from South Korean media, the alliance formed among Apple, TSMC, and Amkor may pose a significant challenge to the South Korean semiconductor giant, Samsung Electronics, potentially creating competition for contracts and drawing close attention from the industry.

Amkor released a statement on November 30, announcing the establishment of the new facility in Peoria, northwest of Phoenix, Arizona. The construction is expected to commence in the second half of 2024, focusing primarily on advanced packaging requirements for high-end chips related to IoT, automotive electronics, 5G, artificial intelligence (AI), and high-performance computing (HPC). The facility has already secured orders from major players, with Apple being its first and largest customer.

Coincidentally, TSMC is also in the process of constructing an advanced process semiconductor wafer facility in Phoenix. 

TrendForce’s research has indicated that the current maximum capacity plan for TSMC’s Arizona plant is around 50,000, with 20-30,000 allocated for 4nm and 3nm each. It is anticipated that the expansion to this scale will only occur after 2027. This capacity is expected to cater to a limited number of domestic customers in the United States who require fully American-made semiconductor products.

Business Korea’s report also suggests that the alliance formed among Apple, TSMC, and Amkor may impact Samsung. Samsung’s second wafer facility in the U.S., located in Taylor City, Texas, is anticipated to start production in the second half of 2024, setting the stage for potential chip procurement battles with TSMC.

Speculations have arisen about Samsung possibly establishing a testing and packaging facility in Taylor City, following the strategy of strengthening vertical integration to enhance competitiveness and gain an advantage in chip procurement.

In November of this year, Samsung unveiled a new strategy called “GDP,” focusing on Gate-All-Around (GAA) transistor technology, DRAM, and 3.5D advanced packaging. The company has pledged to achieve a goal where more than half of its wafer foundry revenue comes from AI chip orders within five years.

(Photo credit: TSMC)

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