According to sources cited in a report from Commercial Times, in response to the global increase in chip orders and rapid AI development, TSMC is actively seeking available land to keep its most advanced process technologies in Taiwan.

Currently, TSMC has already planned three 2nm fabs at the Nanzih Technology Industrial Park in Kaohsiung, southern Taiwan.

Regarding the need for additional land to accommodate facilities for more advanced nodes beyond 2nm, the report notes that the Kaohsiung City Government has been proactively preparing by evaluating land availability, as well as water and electricity supply, for TSMC’s next-generation advanced technology production, specifically targeting the A14 (14 angstrom) process.

Yet, regarding the matter, TSMC has remained discreet and declined to comment on market rumors regarding the progress of expansion.

Reportedly, the Nanzih Park site has the capacity to accommodate up to five fabs for TSMC, and there are rumors that its fourth and fifth fabs are likely to focus on A14 process, although TSMC has yet to confirm this.

TSMC’s first 2nm process fab in Nanzih is expected to begin mass production in 2025. Per sources cited by the report, the node will be used in high-performance computing (HPC), smartphones, electric vehicles, and autonomous driving applications.

Earlier, concerns were raised about the progress of TSMC’s CoWoS advanced packaging plant due to the discovery of cultural heritage sites at the Chiayi Science Park.

However, sources cited by Commercial Times have pointed out that while there have been some delays due to cultural heritage issues, TSMC’s adjustment plan has been approved. The company will adjust its working procedures in order to proceed with construction according to the original schedule, with no changes to the completion timeline.

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(Photo credit: TSMC)

TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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