With Trump’s inauguration in January, “Made in America” is expected to dominate, driving an urgent push for semiconductor packaging and equipment companies to relocate to North America. Coupled with TSMC’s Arizona plant set to start mass production early next year, the Commercial Times reports that industry insiders foresee a surge in investments across the North American semiconductor supply chain.

TSMC’s Arizona fab is in the final stages of preparing for 4nm production, with a projected monthly capacity of 20,000 to 30,000 wafers. The company previously signed an MOU with Amkor Technology, a partnership widely seen as supporting advanced and back-end packaging efforts.

On November 8, however, leading packaging and testing company ASE also announced plans to set up a facility in Mexico, aiming to offer advanced packaging services for TSMC’s U.S.-produced chips.

Industry sources cited by Commercial Times speculate that ASE’s Mexico plant, once complete, could compete with Amkor for TSMC’s packaging and testing orders from the Arizona fab. Following the packaging process, the chips could be delivered directly to U.S.-based OEM/ODM partners, including Foxconn, Wistron, and Inventec, for final product assembly, completing the “Made in America” manufacturing chain.

The report also highlights TSMC’s stronghold on advanced packaging technologies such as 3D Fabric and SoIC, required for 2nm production, as well as SoW (system-on-wafer) technology. To meet customer demands, TSMC may need to establish in-house advanced packaging capabilities in the U.S. for even more advanced processes.

TSMC’s advanced packaging line is already highly automated, with optimized production flows reduced from over 300 steps to just over 200, and its gross margin is approaching the company average. The Commercial Times quotes industry experts who suggest that setting up advanced packaging capacity in the U.S. should be straightforward for TSMC, given its extensive experience in wafer fab construction, making it a matter of time.

(Photo credit: TSMC)

Driven by booming demand for AI chips, TSMC’s advanced CoWoS (Chip on Wafer on Substrate) packaging faces a significant supply shortage. In response, TSMC is expanding its production capacity and is considering price increases to maintain supply chain stability.

According to a recent report from Morgan Stanley cited by Commercial Times, TSMC has received approval from NVIDIA to raise prices next year, with CoWoS packaging expected to increase by 10% to 20%, depending on capacity expansion.

At TSMC’s Q3 earnings call, Chairman C.C. Wei highlighted that customer demand for CoWoS far outstrips supply. Despite TSMC’s plan to more than double CoWoS capacity in 2024 compared to 2023, supply constraints persist.

To meet demand, TSMC is collaborating closely with packaging and testing firms to expand CoWoS capacity. Industry sources quoted by CNA reveal that ASE Group and SPIL are working with TSMC on the back-end CoWoS-S oS (on-Substrate) process. By 2025, ASE may handle 40-50% of TSMC’s outsourced CoWoS-S oS packaging.

ASE announced investments in advanced packaging, covering CoWoS front-end (Chip on Wafer) and oS processes, along with advanced testing.

SPIL, a subsidiary of ASE, recently invested NT$419 million in land at Central Taiwan Science Park’s Erlin Park, boosting CoWoS capacity. Additionally, SPIL has allocated NT$3.702 billion to acquire property from Ming Hwei Energy in Douliu, Yunlin, for further expansion.

ASE also announced in early October that its new Kaohsiung K28 facility, slated for completion in 2026, will expand CoWoS capacity.

In early October, TSMC announced a partnership with Amkor in Arizona to expand InFO and CoWoS packaging capabilities. Industry sources cited by CNA suggest that Apple, a user of TSMC’s U.S.-based 4nm process for application processors, may leverage Amkor’s CoWoS capacity. Other U.S.-based AI clients utilizing TSMC’s advanced nodes for ASICs and GPUs are also expected to consider Amkor’s CoWoS packaging in the future.

(Photo credit: TSMC)

To turn adversity around, Intel launched its latest AI accelerator, Gaudi 3, in late September. However, a report by the Economic Daily News indicates that the struggling giant has significantly slashed the chip’s shipment targets by over 30% for next year, which may severely impact orders for its Taiwanese supply chain.

According to the report, the move could be attributed to the Intel’s internal strategy adjustments and the fluctuation of customer demand, which prompts it to cut orders on Taiwanese companies such as TSMC, ASE Technology, and ASIC firm Alchip.

According to industrial sources cited by the report, Intel originally projected to ship 300K to 350K units of Gaudi 3 in 2025. However, the target has now been revised to 200K to 250K units, marking a reduction of more than 30%.

According to the report, after acquiring Israel-based AI chip company Habana Labs in 2019, Intel seems to be relatively conservative about their co-development of the next-gen AI accelerators. Intel’s cautious attitude is evident from its recent moves, such as expediting the conclusion of previous projects like Gaudi 2, as well as lowering the shipment target for Gaudi 3 next year.

Intel declined to comment on the matter, the report notes.

According to industrial sources cited by the report, the adjustment will pose limited impact to TSMC, which manufactures Intel’s Gaudi 3 with its 5nm node. While the demand for the foundry leader’s advanced nodes remains robust, other customers are expected to quickly fill the gap left by Intel.

In terms of IC packaging and testing services provider ASE and its subsidiary SPIL, as they also have a diversified client portfolio, with major tech companies placing orders, the capacity can be swiftly reallocated to minimize the impact, the report suggests.

Nevertheless, for those with smaller scales and a higher client concentration, the impact may be more significant. Taiwanese ASIC firm Alchip, which provides ASIC design services for Intel’s Gaudi 2 and Gaudi 3, therefore, may be more vulnerable to Intel’s potential shipment reduction, according to the report.

Unimicron, which serves as the primary supplier of substrates for Intel’s chips, may also be impacted by the fluctuation of Intel’s orders, the report notes. However, when asked about the potential impact, the company reaffirms its optimistic outlook regarding the second half of 2024, as it expects the demand for AI accelerators and optical modules to be stronger than the first half.

Currently, NVIDIA still holds the throne in the global AI chip market, with rivals such as AMD and Intel eagerly trying to catch up.

Intel’s latest effort, Gaudi 3, boasts 64 Tensor processor cores (TPCs) and eight matrix multiplication engines (MMEs) to accelerate deep neural network computations, and is specifically optimized for large-scale generative AI, according to its press release. It even claims to offer double the performance at the same cost compared to NVIDIA’s H100, the report says.

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(Photo credit: Intel)

The surging global demand for AI chips is straining advanced packaging capacity, driving a sharp focus on fan-out panel-level packaging (FOPLP) within Taiwan’s semiconductor industry. According to a report by Commercial Times, major packaging and testing firms such as ASE and Powertech, alongside equipment manufacturers like Gudeng, GPTC, E&R Engineering, Mirle, and analysis firm MAtek, are investing heavily in FOPLP technology.

The rapid development and expanding applications of AI chips have intensified the need for higher chip performance, smaller sizes, better heat dissipation, and lower costs. As emerging applications such as 5G, AIoT, and automotive chips continue to grow, the demand for high-performance, high-power semiconductors has surged. FOPLP technology, which enhances performance while significantly cutting costs and addressing thermal and signal integration issues, is emerging as a key trend in the market.

ASE has been working on panel-level packaging for several years. The company expects its panel-level packaging equipment to be in place by the second quarter of 2025, maintaining a technological edge. On October 2, ASE announced a nearly NT$8 billion purchase of equipment by its subsidiary, SPIL, from companies including Advantest.

Powertech has already moved into wafer-level fan-out packaging and is now shifting toward panel-level fan-out packaging. The company claims that the new technology can increase chip area output by two to three times. It has dedicated its Hsinchu plant to panel-level fan-out packaging and TSV CIS, positioning itself for future growth opportunities.

Equipment manufacturers are also seeking to capitalize on this trend. GPTC, a supplier to major foundries for InFO packaging, is expected to benefit from future FOPLP opportunities due to the similar nature of its equipment. Gudeng Precision is developing panel-level packaging transport boxes, with mass production expected in 2025.

FOPLP combined with TGV drilling is seen as the key to this technology. Analysts cited by Commercial Times highlight that FOPLP+TGV enables higher area utilization and unit capacity, which effectively reduces heterogeneous packaging costs.

E&R Engineering is focusing on drilling, testing, and cutting equipment for glass substrates, primarily supplying panel manufacturers in Taiwan and outsourced assembly and testing providers in Southeast Asia. Mirle has targeted glass substrate transport equipment, while MAtek is leading the market in glass substrate inspection technology.

(Photo credit: ASE)

According to a report by the Commercial Times, while TSMC, the global foundry leader, has established a plant in Kikuyo, Kumamoto City, Kyushu. ASE Technology Holdings (ASE), a giant in packaging industry, is setting up a plant in Kitakyushu as well. With these developments, Japan’s semiconductor production could potentially integrate both front-end and back-end processes, forming a cluster within Kyushu.

This development could lead to a revival of Kyushu’s semiconductor industry, once known as the “Silicon Island” in Japan, attracting more semiconductor supply chain companies to the region.

The report further notes that related equipment and inspection company, including MA-tek, semiconductor transmission and storage solutions provider Gudeng Precision, and semiconductor material distributor Topco Technologies Corp. (Topco) have all established bases in Kumamoto.

MA-tek, a leader in semiconductor inspection and analysis services, established its first Japanese laboratory in 2019 and a second one in Kumamoto in 2023. Since their establishment, these laboratories have consistently achieved growth rates higher than the company average.

With the rise of AI applications, many Japanese clients have AI chip development projects, leading to increased demand for MA-tek’s materials analysis (MA) and advanced process inspection services.

To capitalize on advanced process and packaging opportunities brought by AI, the company MAT has decided to increase its capital expenditure this year to between NTD 1.2 billion and NTD 1.4 billion.

These funds will be used to expand and upgrade the testing equipment and laboratory facilities in Nagoya and Kumamoto, and to establish a third laboratory in Hokkaido, which is expected to start contributing to revenue in Q1 2025.

On the other hand, Gudeng Precision is also planning to build a new plant in Kurume in Q2 this year, located between Fukuoka and Kumamoto, with a planned area of approximately 3,000 ping (about 10,000 square meters).

Gudeng Precision’s investment in Kurume, Japan, including equipment procurement, is estimated at about NTD 400 million to NTD 450 million. Construction is expected to begin by the end of this year, with production slated to start by the end of 2025.

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(Photo credit: JASM)