ACM Research, Inc., a provider of wafer processing solutions for semiconductor and advanced wafer-level packaging applications in China, announced on September 3rd the release of its Ultra C bev-p panel bevel etching tool for fan-out panel-level packaging (FOPLP) applications.

This new tool is designed for bevel etching and cleaning in copper-related processes, offering dual-side bevel etching for both the front and back of panels within a single system, further boosting process efficiency and enhances product reliability.

Moreover, a day after the announcement, the company further revealed that it had received purchase orders for four wafer-level packaging tools, including two from a U.S.-based customer and two from a U.S.-based research and development (R&D) center.

Dr. David Wang, ACM’s president and chief executive officer, believes that FOPLP will grow in importance as it addresses the evolving needs of modern electronic applications, offering benefits in integration density, cost efficiency, and design flexibility.

Reportedly, the new Ultra C bev-p tool is designed to deliver advanced performance, utilizing ACM’s expertise in wet processing. It is one of the first tools to incorporate double-sided bevel etching for horizontal panel applications.

Together with the Ultra ECP ap-p for electrochemical plating and the Ultra C vac-p flux cleaning tools, the Ultra C bev-p is expected to support the FOPLP market by enabling advanced packaging on large panels with high-precision features.

ACM emphasizes that the Ultra C bev-p tool is a critical enabler for FOPLP processes, employing a wet etching technique tailored for bevel etching and copper residue removal.

This process plays a vital role in preventing electrical shorts, reducing contamination risks, and preserving the integrity of subsequent processing steps, ensuring long-term device reliability. The tool’s effectiveness is driven by ACM’s patented technology, designed to tackle the specific challenges of square panel substrates.

Different from traditional round wafers, ACM’s design is said to ensure precise bevel removal process that stays confined to the bevel region, even on warped panels. This is essential for maintaining the integrity of the etching process while ensuring the high performance and reliability needed for advanced semiconductor technologies.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

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• [News] ACM Research Steps into FOPLP Advanced Packaging Field
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)

With advanced packaging capacity at TSMC being tight, the expansion of CoWoS has garnered significant attention. According to a report from Economic Daily News, Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, noted at SEMICON Taiwan 2024 that the foundry giant is rapidly expanding its advanced packaging capacity to meet customer demands.

The company expects CoWoS capacity to grow at a compound annual growth rate of over 50% from 2022 to 2026, with high-speed expansion continuing at least until 2026.

During Jun He’s keynote at the “3D IC/CoWoS for AI Summit – HIGS Series Event” on September 4, He joked that due to severe supply shortages, he refrained from including numbers in his presentation, as customer complaints about insufficient capacity were frequent.

In response to strong customer demand, Jun He revealed that TSMC will continue to rapidly expand its advanced packaging capacity through 2026, with increased construction speeds. For CoWoS capacity, the time to build an advanced packaging plant has been reduced from three to five years to within two years, or even a year and a half.

He noted that the strong demand for advanced packaging is driven by the cost reduction benefits of chiplet design. The successful development of chiplets relies on advanced packaging, prompting TSMC to actively promote the 3DFabric Alliance to accelerate innovation and development within the 3D IC ecosystem.

Mike Hung, Senior Vice President of ASE echoed Jun He’s views, noting that the industry has learned valuable lessons from the 2.5D packaging sector since its mass production in 2013. ASE has been partnering with TSMC to boost their CoWoS capacities.

He added that further standardization of equipment or materials would be advantageous for accelerating industry innovation.

Take panel-level packaging as an example, he noted that while the technology could help  increased efficiency thanks to the transition from round to square substrates, it also presents challenges in areas like equipment and materials.

Jun He added that advancing packaging requires efforts from partners in advanced packaging materials and HBM to drive progress collectively.

On the other hand, DJ Lee, Director and COO of PCB leader ZDT Group, suggested that as the industry progresses, packaging substrates will trend towards higher layers, larger areas, flatness, and precise designs. To meet the semiconductor-level requirements, substrate manufacturers will need to enhance their smart manufacturing capabilities.

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• [News] TSMC Rumored to Build New CoWoS Plant in Southern Taiwan
• [News] TSMC Halts Chia-Yi Plant Construction Due to Relic Found, Quickly Initiates Preparation for 2nd Plant

(Photo credit: TSMC)

Recently, Samsung Electro-Mechanics announced that by 2026, the sales share of its high-end Flip Chip Ball Grid Array (FCBGA) substrates for server and artificial intelligence will exceed 50%.

FCBGA is an integrated circuit (IC) packaging technology，which involves flipping the chip and connecting it to the packaging substrate, then using spherical solder bumps to attach the package to the substrate.

It is mainly used in the packaging of high-density, high-speed, multi-functional large-scale IC chips, offering advantages such as high integration, small size, high performance, and low power consumption.

After a prolonged period of inventory cutting, the balance between semiconductor supply and demand sides has improved, with market demand gradually recovering.

The strong demand in fields such as high-speed network, server, smart driving, and optical module has continuously energized the development of high-multilayer high-speed boards and advanced HDI boards, which in turn is gradually boosting the prosperity of the packaging substrate industry.

As one of the main packaging methods for core electronic components like PC central processing unit, memory, and graphics processor, FCBGA boasts significant market potential in the development of 5G communications, artificial intelligence, virtual reality, and other fields.

Globally, IDM companies such as Micron, Infineon, and NXP have conducted extensive research and development in the FCBGA packaging field, while specialized packaging and testing companies like ASE Group, JCET, and Amkor have also developed various FCBGA technologies.

It is reported that numerous major international semiconductor companies, including Intel, Qualcomm, NVIDIA, AMD, and Samsung, are utilizing FCBGA technology.

Intel is one of the pioneers of FCBGA technology, first applying it to processors in 1997, while Apple is a loyal adopter of FCBGA technology, having used it in its processors from an early stage.

Data indicates that the global FCBGA packaging technology market will continue to grow rapidly in the coming years, with the market size expected to exceed USD 20 billion by 2026.

In face of such a highly potential opportunities, an increasingly more companies are channeling more efforts in developing FCBGA packaging technology, continuously facilitating its innovation and upgrade, and Chinese companies are also a part of this competition.

Currently, main companies engaging in FCBGA packaging substrates business in China include Fastprint, SCC, and FHEC (Forehope-elec), etc, which have disclosed their current progresses referring to FCBGA research and development.

Besides, Strongteam, a real estate company attempting to enter the semiconductor field, has set its sight on the FCBGA sector.

Fastprint disclosed that its low-layer FCBGA packaging substrates are currently in the small-batch delivery stage, with primary applications in the automotive and AI sectors.

SCC stated that it already has the capability of mass producing FCBGA packaging substrates with 16 layers and less, and the capability of sample manufacturing products with more than 16 layers.

The production line validation, sample delivery, and certification processes for various product levels have proceeded smoothly on track. Strongteam is actively transitioning into the semiconductor field and plans to invest in high-end FCBGA IC substrate enterprises.

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• [News] Samsung Gains Early Market Entry Advantage in the Panel-Level Packaging Sector Ahead of TSMC
• [News] Intel Foundry Unveils its Expanded Process Roadmap for AI Era at Direct Connect 2024 Event

(Photo credit: Samsung)

Per a report by the Vietnam News Agency, Vietnamese Prime Minister Phạm Minh Chính recently signed Government Decree No. 791/QĐ-TTg on the establishment of the National Steering Committee for Semiconductor Industry Development.

The main tasks and functions of the steering committee include assisting the Prime Minister and the government in researching, guiding, and coordinating the resolution of important and cross-departmental matters related to promoting the development of Vietnam’s semiconductor industry; researching, consulting, and advising on directions and solutions to promote the industry’s growth; and guiding the coordination among various departments, government agencies, relevant organizations, and entities to vigorously advance the development of Vietnam’s semiconductor industry.

Semiconductor industry is one of the strategically important global industries, and it undoubtedly represents a significant development opportunity for Vietnam.

It is reported that the semiconductor, as one of Vietnam’s nine national-level products, has been included in the country’s key development priorities for the next 30 to 50 years.

According to its National Semiconductor Industry Strategy, Vietnam aims to become a global center for semiconductor chip design, packaging, and testing by 2030.

To achieve this goal, the Vietnamese government has introduced a series of preferential policies and incentives to encourage foreign enterprises to invest in the country.

Moreover, the government has established the National Innovation Center (NIC) to create a high-tech ecosystem and beef up the training of professionals to meet the needs of developing semiconductor industry.

Currently, Vietnam has drawn in investment from foreign enterprises such as Intel, ASE Group, Samsung Electronics, Amkor, Qualcomm, ONSemi, Renesas, Texas Instruments, NXP, Marvell, Synopsys, Hana, and Anpei. In fact, with global capital investment, Vietnam’s semiconductor industry ecosystem is gradually taking shape in recent years.

Vietnam’s Minister of Planning and Investment Nguyễn Chí Dũng stated that Vietnam boasts some conditions and factors conducive to the development of semiconductor industry, involving a stable political system, a favorable geographical location, and attractive investment incentive policies.

The Vietnamese government has been committed to developing semiconductor industry and hopes to attract more and more large enterprises to invest in Vietnam.

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• [News] Nvidia CEO Visits Vietnam, Plans to Establish Chip R&D Base

(Photo credit: Intel)

TSMC continues to showcase its drive in the advanced packaging market. According to a report from MoneyDJ, TSMC has forecasted that CoWoS will remain in high demand through 2025, with potential for capacity to double in two consecutive years. TSMC is also entering the FOPLP (Fan-Out Panel-Level Packaging) space, a technology that OSATs and panel manufacturers have been developing for years, with a goal to launch it in three years.

TSMC’s stronghold on advanced packaging technologies has raised market concerns that OSATs may see their opportunities diminished as TSMC consolidates its market position.

During its earnings call, TSMC introduced “Foundry 2.0,” a new definition for the semiconductor manufacturing industry. This expanded definition now includes not only foundry services but also packaging, testing, photomask production, and other integrated component manufacturing, excluding memory production. TSMC further stated that this new definition will better reflect the company’s growing market opportunities and that the company will focus solely on cutting-edge back-end technologies.

Under this new definition, TSMC estimates the Foundry 2.0 industry will be nearly USD 250 billion in 2023, up from the previous estimate of USD 115 billion. With this new scope, the industry is expected to grow by 10% annually in 2024. Additionally, TSMC’s market share in Foundry 2.0 (logic semiconductor manufacturing) for 2023 is revised to 28%, with expectations for continued growth in 2024.

The sources cited by the report has pointed out that, observing TSMC’s process advancements, the 3nm process began mass production in 2022, with the 2nm process set for 2025, indicating a lengthening of the development cycle to three years.

Regarding the aforementioned nodes, advanced packaging may help enhance performance, reduce costs, and has the advantage of binding high-end products from top-tier clients. Additionally, the investment required for advanced packaging is significantly smaller compared to frontend technologies, making it a crucial area of focus.

The report continues to note that TSMC currently retains the majority of major CoWoS orders and collaborates with OSATs in the WoS segment. However, TSMC has reportedly yet finalized its CoW segment outsourcing orders.

Meanwhile, AMD and NVIDIA have reportedly turned to Amkor and ASE’s subsidiary, Siliconware, for CoWoS-related products, focusing on cost-sensitive high-performance products. Amkor is expected to supply about 70,000 to 80,000 units annually this year, while Siliconware can provide about 50,000 to 60,000 units.

Additionally, OSATs have been confined to mature IC FOPLP technologies for the past 7-8 years, whereas TSMC has announced it will launch its own FOPLP technology in three years.

TSMC’s planned FOPLP is a rectangular CoWoS-L concept, offering advantages in low unit cost and large-size packaging. However, it faces physical limitations such as issues in coating, spinning, and warping. TSMC, backed by a substantial equipment and materials supply chain, is well-positioned to address these challenges.

As for opportunities for other OSATs, the advanced packaging market is actually vast and can be broadly categorized into flip-chip, fan-out, fan-in, 2.5D/3D, and embedded die packaging.

These technologies can be integrated, and OSATs are not limited to TSMC’s top-tier Info, CoWoS, or SoIC technologies. OSATs can offer more cost-effective advanced packaging solutions compared to fabs, providing competitive alternatives in terms of cost and performance.

Read more

• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Introduces “Foundry 2.0” to Include Packaging, Testing, Mask making and Others

(Photo credit: TSMC)