With the surge in new applications like AI, advanced packaging remains a hot topic, particularly with FOPLP (Fan-Out Panel Level Packaging) technology gaining renewed attention. According to sources cited by a report from MoneyDJ, leading semiconductor foundry TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

TSMC introduced the FOWLP (Fan-Out Wafer Level Packaging) technology named InFO (Integrated Fan-Out) in 2016, first used in the iPhone 7’s A10 processor. Subsequently, assembly and testing facilities actively promoted FOPLP solutions, looking to attract customers with lower production costs, yet faced ongoing technical challenges. Therefore, current terminal applications remain within mature processes, such as PMIC (Power Management IC) products.

However, per the sources cited by the same report, TSMC’s move to transition advanced packaging technology from wafer level to panel level is more than just talk—it’s becoming a reality. It is reported that TSMC is planning to use rectangular substrates measuring 515mm by 510mm, with a dedicated team already conducting research and planning to establish a mini line.

The source further mentioned that, TSMC’s development of FOPLP can be seen as a rectangular version of InFO, offering advantages such as lower unit costs and larger package sizes.

This advancement could further integrate other technologies on TSMC’s 3D fabric platform, paving the way for 2.5D/3D advanced packaging solutions to serve high-end product applications. This approach could be regarded similar to a rectangular CoWoS, currently targeted at the AI GPU sector with NVIDIA as a customer. If progress continues smoothly, these developments could potentially debut between 2026 and 2027.

On the AMD front, it is understood that their initial partners for FOPLP are ASE Technology and PowerTech Technologies, with potential applications in PC or gaming console chips. Reportedly, it’s suggested that previous packaging methods for PCs and gaming consoles primarily used FC-BGA, but upcoming new products may potentially upgrade to CoWoS level.

Sources cited by the report note that in the early stages of FOPLP, players like PowerTech Technologies, Innolux, and ASE Technology faced challenges and intermittent demand. To allocate resources effectively, equipment suppliers have been conservative in their investments in related fields, focusing mainly on adjusting specifications to meet customer demands. With TSMC now officially joining, equipment suppliers are shifting to a more proactive stance in preparation for upcoming developments.

In summary, the development of the FOPLP ecosystem hinges largely on TSMC’s role. TSMC is expected to maintain leadership in the high-end segment, while packaging and testing firms will cater to the mid-to-high-end markets. Semiconductor experts believe that in the realm of high-speed computing, CoWoS will remain mainstream for the next 3 to 5 years, with advanced 3D packaging like SoIC gaining prominence in high-end applications, solidifying TSMC’s position as a key player.

For packaging and testing companies, the key lies in product upgrades that offer cost-effectiveness. The success of FOPLP as the next generation of advanced packaging hinges on how chip manufacturers position their products, address yield issues related to warpage, and ensure overall performance and pricing that justify customer investment.

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(Photo credit: TSMC)

On June 21, ASE Group announced that ASE Semiconductor will collaborate with Hung Ching Construction to build a K28 plant in Kaohsiung. The project is expected to be completed in the fourth quarter of 2026 and will focus on end testing of advanced packaging processes, and high-performance computing for artificial intelligence (AI) chip.

ASE’s CFO Dong Hongsi introduced that for the K28 plant construction project, ASE Semiconductor will provide the land it held in Kaohsiung while Hung Ching Construction will provide fund support. The plant will have one basement level and seven above-ground floors. As to the rights and value distribution between the two parties, ASE Semiconductor and Hung Ching Construction will respectively hold a share of 22.24% and 77.76%. Upon completion, ASE Semiconductor or its subsidiaries will have the first purchase rights for Hung Ching Construction’s property ownership.

It was reported previously that as an important part of the company’s operational plans, ASE’s Kaohsiung plant had purchased land in Tashe for phased development in a bid to  address the demands for end testing of advanced packaging processes, AI chip high-performance computing, and heat dissipation needs. Phase one, the K27 plant, was completed in 2023, primarily setting up Flip Chip and IC testing production lines.

At a financial result briefing in February this year, ASE stated that to expand advanced packaging capacity, this year’s overall capital expenditure will increase by 40% to 50%, reaching a historical high. Of this, 65% will be allocated to packaging, especially advanced packaging projects, with over 60% used for packaging testing and 30% for electronic manufacturing services.

Moreover, ASE is optimistic about the potential of AI technology and expects AI revenue contributions to double to USD 500 million by the end of 2024 compared to 2023. AI-related revenue is expected to account for a single-digit percentage of the total ATM (Packaging and test) business this year, surpassing last year’s low single digit. And the industry anticipates that next year’s proportion could reach a high single-digit percentage.

Advanced packaging industry has been in high gear in recent years, and ASE has made significant investment in this area over the past two years. In February this year, Infineon and ASE announced that ASE would invest approximately TWD 2.1 billion to acquire Infineon’s two backend assembly and test plants in Philippines and South Korea. This acquisition aims to expand ASE’s  power chip module packaging & test and lead frame packaging for automotive and industrial automation applications, with the transaction expected to be completed by the end of 2Q24.

On January 19, ASE announced that its Malaysian subsidiary would invest MYR 69.696 million to acquire land use right in the Gardenia Tech Park in Penang, Malaysia to meet operational needs. Industry analysts believed this investment was primarily for expanding advanced packaging capacity. It was reported that ASE Semiconductor has been actively expanding its packaging and test capacity in Malaysia. In November 2022, its new factories 4 and 5 in Penang broke ground, with construction expected to be completed by 2025.

Additionally, in late December 2023, ASE Semiconductor announced that it had leased the 7th floors of both K21 and K22 buildings from ASE TEST in Kaohsiung’s Nanzi district to expand its packaging capacity. The industry believed that the intention was to increase its advanced packaging capacity for AI chip.

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• [News] ASE Sets Up New Facility in Kaohsiung for Advanced Packaging, Targeting Completion in 2026
• [News] ASE Expands Production at Kaohsiung Plant, Focusing on Advanced Packaging for AI Chips

According to a report from CNA, Taiwanese semiconductor testing and packaging giant ASE announced on June 21st that it will collaborate with Hung Ching Development & Construction Corporation to jointly build the K28 plant in Kaohsiung. Scheduled for completion in Q4 2026, the facility will reportedly focus on advanced packaging and final testing in order to meet the high-performance computing and cooling demands of AI chips.

ASE’s CFO Joseph Tung stated that ASE Semiconductor is planning for operational growth at its Kaohsiung facilities. To meet the demand for advanced packaging processes, high-performance computing for AI chips and cooling, the company is developing land in Dashe, Kaohsiung in two phases. The first phase, K27 plant, was completed and moved-in in 2023, while the K28 plant, the second phase, aims to be completed by Q4 2026.

As reported by CNA citing sources, ASE Kaohsiung Plant contributes approximately 20% to ASE Technology Holding Co., Ltd.’s total revenue. The plant specializes in providing services such as packaging, wafer bumping, probe testing, materials, and final testing. It has also developed several smart factories focusing on advanced processes, including Fan-out packaging, System-in-Package (SiP), wafer bumping, and Flip Chip packaging.

These technologies are primarily used in automotive, medical, IoT, high-speed computing, artificial intelligence, and application processor fields.

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• [News] Following TSMC, ASE Reportedly Plans to Establish Plant in Kumamoto
• [News] ASE Expands Production at Kaohsiung Plant, Focusing on Advanced Packaging for AI Chips

Following TSMC’s announcement of investing USD 20 billion to build two plants in Kumamoto, Japan, industry sources cited by a report from Commercial Times has indicated that the major global semiconductor assembly and testing provider, ASE Group, is in discussions with the Japanese government to finalize subsidies and investment details.

Reportedly, ASE plans to invest nearly NTD 10 billion (roughly USD 306.3 million) to construct its first advanced packaging plant in Kumamoto, becoming the second Taiwanese semiconductor giant to set foot in the region.

Regarding the establishment of a plant in Kumamoto, ASE Group stated that it does not comment on market rumors.

During its earnings call last week, ASE Group announced a capital expenditure increase to expand related capacities due to the upward adjustment in advanced packaging projects. This year’s capital expenditure, originally estimated at around USD 2.1 billion with a year-on-year increase of over 40%, has been raised to a potential 50% increase (up to USD 2.25 billion), potentially reaching a historic high.

The semiconductor industry is witnessing a great era of global competition with various countries pouring money into subsidies. Recently, there have been rumors of the Japanese government actively reaching out to Taiwanese semiconductor companies and offering substantial subsidies, aiming to build a complete semiconductor industry chain covering upstream, midstream, and downstream sectors.

Apart from TSMC’s decision to establish two advanced semiconductor plants in Kumamoto, Intel is also considering establishing an advanced packaging research institution in Japan, and Samsung is planning to set up advanced packaging research facilities in Yokohama.

Industry sources cited by the same report point out that these signs have indicated that after mastering wafer manufacturing technology, the next phase for Japan is to enhance the establishment of the packaging industry.

Industry rumors have recently circulated that the Japanese government has been in discussions with senior executives from ASE Group for some time, and the relevant subsidy and investment details are generally agreed upon. The location for the new facility is expected to be in Kumamoto, near TSMC’s upcoming plant. As per the same report citing sources, there is a chance that ASE’s Kumamoto facility, like TSMC’s second plant in Kumamoto, will be planned to start production before the end of 2027.

In fact, as early as 2004, ASE Group acquired full ownership of an IC packaging and testing facility in Yamagata Prefecture, Japan, from NEC for USD 80 million. However, over the past two decades, Japan’s influence in the global semiconductor sector has waned, and ASE’s acquisition of the NEC facility has not made significant operational contributions.

ASE Group’s global footprint currently includes high-end product bases in Taiwan, as well as its packaging and testing capacities in China, Japan, Malaysia, South Korea, and Singapore.

ASE is continuing its expansion efforts in Taiwan, including Kaohsiung, Zhongli, and Tanzi. Evenmore, on February 22nd, ASE Group and semiconductor giant Infineon Technologies jointly announced the finalization of an agreement. ASE Group will invest EUR 62.589 million to acquire Infineon’s backend packaging facilities located in Cavite, Philippines, and Cheonan, South Korea.

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“It is not the shortage of AI chips, it is the shortage of our CoWoS capacity,” replied TSMC Chairman Mark Liu during an interview in September last year, propelling this technology that TSMC had quietly cultivated for over a decade into a global spotlight.

As per a report from TechNews, the hardware demand sparked by generative AI has also led to “advanced packaging” becoming not only a hot keyword pursued by global investors but also a prominent feature of the semiconductor industry. From foundries and memory manufacturers to OASTs, all are actively involved in the research and capacity expansion of advanced packaging technologies.

TSMC, the leading force in the advanced packaging market, has repeatedly emphasized its efforts to expand capacity during its earnings call, including capacity expansions in Zhunan and Hsinchu, and even the possibility of constructing advanced packaging facilities in Chiayi.

Intel’s strategic moves also underscore its emphasis on the development of advanced packaging. Intel’s new plant completed in Penang, Malaysia in 2023 is aimed at establishing advanced packaging capacity.

Leading packaging and testing company, ASE Technology Holding, has also actively participated in the competition for advanced packaging. Apart from its subsidiary, Siliconware Precision Industries (SPIL), which is already a supplier for the backend packaging of CoWoS, ASE Technology Holding is also expanding advanced packaging capacity at its facility in Kaohsiung.

Memory manufacturers are also aggressively ramping up their advanced packaging capacity. SK Hynix, which exclusively supplies HBM for NVIDIA AI chips, recently announced plans to invest USD 1 billion in the development of advanced packaging. They view advanced packaging as the “future focus of semiconductor development for the next 50 years.

Advanced Packaging: Over a Decade of Development

In fact, advanced packaging is not a new concept. Tracing the history of packaging technology, the year 2000 undoubtedly marked a turning point. From this year onwards, packaging technology shifted from traditional wire bonding and flip-chip methods to “wafer-level packaging,” where most or all packaging and testing processes are conducted on the wafer itself.

The 2.5D packaging, which gained significant attention after 2023, actually emerged as early as 2010. However, due to cost concerns, the number of manufacturers adopting this technology was relatively limited, with a focus on high-performance computing chips.

Chiang Shang-yi, the Chief Strategy Officer of Foxconn Semiconductor, recalled the initial lack of interest in CoWoS technology, which even led to him being regarded as a “joke” within the company( TSMC) for proposing advanced packaging. He also revealed that the first company willing to adopt the costly CoWoS technology was actually Huawei.

▲ Semiconductor Packaging Technology Evolution compiled by McKinsey, Accelerated Technological Evolution after 2000 (Source: McKinsey)

Compared to 2D packaging technology, 2.5D packaging involves placing an intermediate layer between the chip and the IC substrate and stacking different chips in parallel. TSMC’s CoWoS has become synonymous with 2.5D packaging, where a silicon interposer layer is inserted between the chip and the SiP substrate, and metal layers are connected using Through-Silicon Vias (TSVs) to overcome the density limitations of SiP substrates, which previously restricted the number of chips.

Despite TSMC’s dominance, Intel, with its extensive technical expertise in CPU packaging, cannot be underestimated. In the 2.5D packaging battlefield, Intel employs EMIB technology as its strategy. Unlike CoWoS, EMIB does not utilize a silicon interposer layer.

Instead, its key feature lies in the “Silicon Bridge,” buried within the packaging substrate, which connects the bare dies. Intel believes that EMIB offers cost advantages compared to solutions using large silicon interposer layers.

In recent years, Samsung, which has been actively cultivating the semiconductor foundry market, has also ventured into the 2.5D packaging arena. Their proprietary I-Cube technology has traditionally targeted applications in High-Performance Computing (HPC) chips. When Samsung introduced I-Cube4 in 2021, it emphasized the integration of multiple logic dies and HBM placed on a silicon interposer layer, enabling heterogeneous integration into a single chip.

As Moore’s Law approaches its limits and the massive computational demands triggered by generative AI continue to surge, coupled with the trend towards lighter, thinner, and smaller end products, chips are inevitably evolving towards more transistors, greater computational power, and lower power consumption performance.

Therefore, the transition of packaging technology from 2.5D to 3D is undoubtedly an inevitable development.

The difference between 3D and 2.5D packaging lies in the stacking method. In 2.5D packaging, chips are stacked parallelly on an intermediate layer, while in 3D packaging, chips are stacked vertically in a three-dimensional manner.

The advantage of 3D packaging lies in its ability to create more space for transistors within a chip through stacking, shorten the distance between different bare dies significantly, enhance transmission efficiency, and reduce power consumption during transmission.

TSMC, Intel, and Samsung Racing for 3D Packaging Technology

TSMC’s positioning in 3D IC technology is undeniable. Its SoIC technology adopts the wafer-to-wafer bonding technique. SoIC integrates homogeneous and heterogeneous small dies into a single chip, with smaller dimensions and a thinner profile. It can be integrated into 2.5D CoWoS or InFO. From an external perspective, SoIC resembles a universal SoC chip but integrates various functions heterogeneously.

Intel’s layout in 3D packaging revolves around its 3D Foveros technology. Structurally, the bottom layer comprises a packaging substrate, with a bottom wafer placed on top serving as an intermediate layer. Within this intermediate layer, numerous TSVs (Through-Silicon Vias) are present, facilitating connections between the upper chips, modules, and other parts of the system to achieve transmission purposes.

Samsung’s X-Cube 3D packaging technology utilizes TSV processes. Currently, Samsung’s X-Cube test chips can stack the SRAM layer on top of the logic layer, interconnected via TSVs, employing its 7nm EUV process technology.

TSMC’s Comprehensive Ecosystem Strategy

Currently dominating the advanced packaging market, thanks to its acquisition of large contracts for manufacturing NVIDIA AI chips, TSMC is not only continuing to develop more advanced packaging technologies but is also actively promoting its 3D Fabric platform.

In addition to incorporating the three key packaging technologies CoWoS, InFo, and SoIC, this platform has expanded into an industry alliance. It includes participation from EDA, IP, DCA/VCA, memory, packaging and testing suppliers, as well as substrate and testing vendors. The goal is to create a complete 3D Fabric ecosystem, strengthen innovation, and enhance customer adoption willingness.

This alliance has attracted active participation from heavyweight players in the semiconductor upstream supply chain. Even companies traditionally seen as competitors in the packaging and testing sector, such as Amkor, ASE Technology Holding, and Siliconware Precision Industries (SPIL), are members. The comprehensive supply chain has become a significant advantage for TSMC in providing advanced packaging contract manufacturing services.

▲ TSMC’s 3D Fabric Alliance members, including major players from EDA to packaging and testing companies. (Image Source: TSMC)

In comparison, Intel, despite its robust technological expertise developed over many years and its proposition to independently provide wafer manufacturing or testing services, faces a disadvantage in expanding its market share in advanced packaging due to its lack of experience in the foundry market.

On the other hand, Samsung, compared to TSMC, is constrained by its yield issues in advanced processes. This limitation leads IC design companies to prioritize foundries with more stable yields when considering outsourcing comprehensive manufacturing services.

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(Photo credit: TSMC)