The highly anticipated 18th International Microsystems, Packaging, Assembly, and Circuits Technology Conference, also known as IMPACT 2023, took place with grandeur from October 25th to 27th at Hall 1 of Taipei Nangang Exhibition Center. This prestigious event was co-organized by leading institutions in the fields of electronics, including IEEE Electronics Packaging Society (IEEE EPS) – Taipei, International Microelectronics Assembly and Packaging Society (iMAPS) – Taiwan, Industrial Technology Research Institute (ITRI), and the Taiwan Printed Circuit Association (TPCA). Under the overarching theme of “IMPACT on the Future of HPC, AI, and Metaverse,” the conference delved deep into the realm of cutting-edge IC packaging and circuit board technologies that are specifically tailored for next-generation applications in HPC, AI, and the Metaverse.

At the opening ceremony, Dr. Wei-Chung Lo, the Chair of IMPACT 2023, President of iMAPS – Taiwan, and Deputy Director of the Electronic and Optoelectronic System Research Laboratories at the ITRI, noted that the event had attracted over 700 participants, with nearly 30% from overseas. This made IMPACT 2023 the largest industry event for advanced semiconductor packaging technologies in Asia. Dr. Lo expressed gratitude for the support from the IEEE EPS, iMAPS, International Electronics Manufacturing Initiative (iNEMI), and Japanese associates including the International Conference on Electronic Packaging (ICEP) and Japan Institute of Electronics Packaging (JIEP). He also thanked the tremendous support from individuals and organizations across the industry and academia.

Innovations in Critical 3D Packaging Technologies and System-Level Performance Upgrade Will Trigger a Surge of New AI Applications

Following the opening ceremony, plenary speeches were delivered by Dr. Jun He, Vice President of Quality and Reliability and Operations and Advanced Packaging Technology and Service at TSMC, and Dr. Raja Swaminathan, Corporate Vice President at AMD. During his speech, Dr. He emphasized the explosive growth in the 3D packaging technology market, with a projected global market value exceeding USD 100 billion by 2025. Dr. He also highlighted TSMC’s proactive approach in aggressively promoting its “3DFabric” platform, which combines advanced packaging technologies such as SoIC (3D), CoWoS (2.5D), and InFO (2.5D). As a testament to the power of 3D packaging technology, he pointed out that NVIDIA’s latest generation GPU (i.e., the H100) has achieved a remarkable six-fold performance improvement compared to its predecessor (i.e., the A100).

The strong demand for HPC is fueling the extensive commercial adoption of 3D packaging technology. In light of this trend, TSMC plans to expand its cleanroom space for the 3D packaging process, with expectations of more than doubling it by 2025. Furthermore, TSMC is expediting collaborations with ecosystem partners to advance critical 3D packaging innovations. One example is hybrid bonding, which enhances interconnect density. Another example is key innovations in 3D packaging that optimize signal integrity for HBM.

▲Dr. Jun He, Vice President at TSMC, highlights the game-changing impact of 3D packaging technology on NVIDIA’s latest GPU, showcasing a remarkable six-fold performance improvement over its predecessor. The surge in demand for HPC is propelling the extensive adoption of 3D packaging technology across commercial applications. Anticipating this trend, TSMC is set to significantly expand its cleanroom space for 3D packaging, with plans to more than double it by 2025. (Source: IMPACT)

Dr. Swaminathan, Corporate Vice President of AMD, said that the demand for supercomputers and AI performance had previously been growing exponentially, doubling every 1.2 years. However, the growth rate has become even higher recently, doubling within a year. The industry’s primary focus lies in upgrading system-level performance through innovations in high-speed interfaces, advanced packaging, and heterogeneous integration. AMD, in particular, is directing its attention toward improving inter-chip communication and energy efficiency. Leveraging its evolving 3D stacking technology and hybrid bonding packaging, AMD aims to substantially reduce power consumption in inter-chip communication. AMD anticipates that it will achieve a 30-fold increase in HPC and AI training efficiency per watt over the next five years.

In summary, TSMC and AMD, as respective leaders in foundry services and IC design, are focusing on the synergistic relationship between advanced packaging technologies and next-generation AI architectures. They recognize that these two sets of technologies work together to drive substantial improvements in the computing capabilities of semiconductor chips.

▲AMD’s Corporate Vice President, Dr. Raja Swaminathan, stated that the 3D stacking and hybrid bonding technologies being developed by his company can significantly reduce the power consumption of inter-chip communication. AMD also forecasts a 30-fold increase in HPC and AI training efficiency per watt in the next five years. (Source: IMPACT)

Collaborative Design to Spark Major Transformations in AI, and High-Density Heterogeneous Integration Platform to Become Crucial Bridge to Future of Semiconductor Technology

This year’s conference marked the third edition of the IEEE EPS Panel Discussion / Forum, presided over by Dr. C. P. Hung, Vice President of the ASE Group. As a key organizer of the IMPACT conference, the IEEE EPS once again brought together the latest R&D findings and influential speakers to facilitate the exchange of information regarding the most recent trends and technological advancements within the semiconductor and electronics industries.

The inception of the IEEE EPS Panel Discussion has seen a progression of significant themes. The first edition centered on the realm of 5G, followed by the second edition that explored edge computing. Notably, this year’s panel was jointly organized with the IEEE Council on Electronic Design Automation (CEDA). The primary focus of this year’s panel discussion – also known as the IEEE EPS and CEDA Joint Panel – was on ECAD tools capable of optimizing the collaborative design process for chips, packages, and systems.

The idea to join forces with the IEEE CEDA originated from Dr. Bill Chen, Fellow and Senior Technical Advisor at the ASE Group. Delivering his remarks remotely from a different location, Dr. Chen emphasized that although AI and machine learning are still in their nascent stages, significant transformations are anticipated over the next few decades. Dr. Chen stressed that collaborative design will drive the development of AI-related products and applications. This trajectory of development will also necessitate the establishment of an open-source chip ecosystem and standardized interfaces to continuously improve efficiency.

▲Dr. C. P. Hung, Vice President of ASE Group and moderator of the IEEE EPS Panel Discussion, stated that this year’s theme, which was jointly developed with the IEEE CEDA, focuses on ECAD tools that optimize collaborative design across chips, packages, and systems. (Source: IMPACT)

In addition, the IEEE EPS and CEDA Joint Panel specially invited renowned scholars and experts from domestic and international backgrounds. Prominent speakers include Dr. Madhavan Swaminathan, Head of the Department of Electrical Engineering at Pennsylvania State University; Dr. Chih-ming Hung, MediaTek’s Assistant Vice President of Technology; Dr. Arvind Sundarranjan, Managing Director at the Applied Packaging Development Center (APDC); Dr. Kyu Lim Sung, Professor at the Georgia Institute of Technology; Dr. Debendra Das Sharma, Intel’s Senior Fellow; and Nan Wang, Vice President of Component Quality and Technology at Cisco.

Dr. Madhavan Swaminathan stressed that high-density heterogeneous integration platforms will be a future trend. Moreover, such platforms have to incorporate a wide range of technologies from antennas to AI to support applications related to network communication and edge computing. This means that R&D and collaborative design also have to take place simultaneously across various fields, with distributed computing and telecommunication solutions playing crucial roles. On the topic of AI-assisted design, Dr. Hung from MediaTek discussed the importance of synergy among material technology, mechanical engineering, EDA tools, etc. However, Dr. Hung also noted that not all advances in these fields have immediate practical uses in the development of AI applications. In the case of 3D AI machine learning, the maturity of the tools for training needs to be considered.

Turning to the topic of hybrid bonding, Dr. Madhavan Swaminathan pointed out that it is a key technology in advancing AI and HPC, as it brings about computing solutions that can handle massive amounts of data with reduced latency and greater power efficiency. On the other hand, hybrid bonding is a highly complex manufacturing process that involves at least hundreds of steps. Optimizing individual steps one at a time is not enough; synergistic progress has to take place across numerous sections of the process in order to raise the yield rate.

Dr. Sung believes that initiating the next wave of the “AI revolution” will require collaborations among various types of chips, and EDA tools provide the necessary support for the development of 2.5D and 3D packages. Besides being the indispensable assistant for chip designers, EDA tools can also contribute to decision-making regarding materials and bonding methods.

As for how the UCIe standard can contribute to the expansion of the ecosystem for small-sized chips, Dr. Debendra Das Sharma said that UCIe allows for the mixing and matching of multiple chips at the package level to overcome manufacturing limitations and increase yield rates. Currently supporting 2D and 2.5D packages, UCIe will also be introduced to 3D packages in the future. When building SoCs, this standard enables innovations at the package level, integrating not only CPU, GPU, and memory but also supporting interfaces such as USB, PCIe, and CXL. The adoption of UCIe is expected to result in dynamic and configurable systems.

Likewise, when discussing the topic of heterogeneous integration, Cisco’s Vice President Wang, mentioned Open Platform Communications (OPC), a set of standards and specifications for industrial telecommunication. Wang said that co-packaged optics, which falls under OPC, can effectively address the challenges related to power consumption and costs associated with the increasing demand from machine learning networks for high-speed connectivity and high-volume computing capability. With OPC technologies, optical components can be closely integrated with Ethernet switch ICs and packaged on the same substrate, thereby reducing system power consumption by as much as 30%. However, the adoption of OPC will bring new challenges related to the integrity of signals and power supply. Hence, collaborative design and system-level optimization are necessary to achieve large-scale application.

▲The IEEE EPS and CEDA Joint Panel featured a strong lineup of speakers. From left to right: Yao-wen Chang, Dean of the College of Electrical Engineering and Computer Science at National Taiwan University; Dr. Arvind Sundarranjan, Managing Director at the APDC; Dr. Chih-ming Hung, MediaTek’s Assistant Vice President of Technology; Dr. Madhavan Swaminathan, Head of the Department of Electrical Engineering at Pennsylvania State University; Dr. C. P. Hung, Vice President of ASE Group; Nan Wang, Vice President of Cisco; Dr. Kyu Lim Sung, Professor at the Georgia Institute of Technology; and Dr. Debendra Das Sharma, Senior Fellow at Intel. (Source: IMPACT)

Seeking the Best Collaborative Design Tools to Rapidly Address the Needs in the Market for Heterogeneous Integration Solutions

In the second half of the joint panel, Dr. Yao-wen Chang, Dean of the College of Electrical Engineering and Computer Science at National Taiwan University, took over as the moderator. He raised three questions for the experts to discuss and share their insights. The first question he posed was, “How can AI and advanced packaging technologies address the most challenging issues in the development of applications related to AI and edge computing?” Dr. Swaminathan from Penn State was the first to respond, explaining that AI requires large-scale computing and thus requires cooperation among chips made with different process nodes. This also means that advanced packaging technologies can facilitate the integration of various types of chips, including RF chips, GPUs, CPUs, and even optical components.

Dr. Hung from MediaTek cited successful cases of AI being applied to power supply analysis and chip layout optimization. However, the bottleneck in advancing 3D integration lies in the lack of data, so AI cannot fully replace humans in designing chips at the present moment. Dr. Sung also pointed to insufficient data related to circuit designs. This impose limitations in supervised learning. Currently, the academic community is ramping up research efforts in unsupervised learning and reinforcement learning. Cisco’s Vice President Wang said heterogeneous integration could address certain challenges in the development of network systems, but he also acknowledged that chip design and chip manufacturing could become more complex as a result.

▲IMPACT 2023 was a major gathering of elites in the semiconductor and electronics industries. The event attracted a huge number of professionals from various sectors to come to the venue and exchange market intelligence and ideas. (Source: IMPACT)

The second question was, “What are the key technological challenges that we must overcome when the next generation of AI interacts with human intelligence? And when can we expect to see solutions to these challenges?” In response to this question, Dr. Das Sharma said that heterogeneous integration can combine processors and memory in a single package, while 3D stacking can further narrow the distance of inter-chip communication, thereby leading to a faster data transfer rate, better performance, and less power consumption. Dr. Sundarrajan also pointed out that solving the challenges of heterogeneous integration will necessitate technological innovations in materials and other areas. Reducing the space between the chip and the substrate, lowering the defect rate, finding ways to strengthen the bond between different materials, and eliminating chip warping are some of the issues mentioned in the joint panel. These kinds of solutions are required to enable chips to achieve the most optimal performance.

The final question posed by Dr. Chang was, “Regarding EDA tools, what is the extent of their readiness for advanced packaging? And what are the major technological gaps that require immediate attention?” In answering this question, Dr. Sung said that the development of EDA tools is somewhat lagging behind when it comes to heterogeneous integration and the construction of 2.5D and 3D packages. Overall, chip designers need more functionality and automation from their EDA tools. While tools for 2D packages are quite mature, there is still considerable room for improvement in designing chips featuring 3D integration. Dr. Madhavan Swaminathan added that current providers of EDA tools tend to be too passive. They are reluctant to invest in new technologies without specific orders from customers. Swaminathan believes EDA companies need to partner with other technology developers to push forward heterogeneous integration.

Dr. Hung stated that even for 2D packages, chip design companies need to have their own in-house tools to address the shortcomings of commercial EDA tools from external providers. Dr. Hung believes EDA companies should respond more promptly to the needs of IC design houses. Turning to Dr. Das Sharma, he stated that when EDA companies see market potential, they will invest in new technologies. The key is to make them recognize that the aforementioned technologies represent the next major direction in the evolution of chip designs. Lastly, Cisco’s Wang called attention to the different integration and analytical capabilities that EDA tools and systems have to have in order to prepare for the potential issues that may arise in the future development of heterogeneous integration. Early preparations are essential.

▲The IEEE EPS and CEDA Joint Panel primarily delved into discussions on the following topics: (1) the use of AI and advance packaging technologies for resolving issues in the development of edge computing and AI-driven applications; (2) the major technological challenges in the development of next-generation AI; and (3) the use of EDA tools to further improve the designs of advanced packages. (Source: IMPACT)

As a collaborative effort between its organizers and a consortium of partnering entities, IMPACT 2023 unfolded as a massive three-day convention, featuring 33 sessions comprising seminars, panel discussions, lectures, and more. The event not only included keynote presentations by top executives from companies like TSMC and AMD but also assembled hundreds of heavyweight experts from academia and accomplished professionals from various industries worldwide. Additionally, the IEEE EPS and CEDAS Joint Panel was held for the first time, offering attendees an in-depth look into the realm of AI-based collaborative design. Embracing a holistic approach, IMPACT 2023 transcended mere technological discourse to explore the contours of market trends, igniting the sparks of innovation that promise to shape our future.

It is worth noting that TPCA Show 2023 was held concurrently, featuring 1,386 booths set up by companies around the world. More than 480 international brands were showcasing their products and services at this event. In terms of thematic focus, the exhibitions at TPCA Show 2023 were primarily about semiconductors (i.e., chip assembly and packaging), net-zero emissions, smart manufacturing, and forward-looking solutions. The organizers of TPCA Show 2023 were eager to provide a wide range of services to foreign visitors as they sought to make the event the premier international platform for presenting the latest innovations and trading cutting-edge solutions. Like IMPACT, TPCA Show aims to promote the development of various industries. These events also continue to demonstrate Taiwan’s capabilities in the areas of PCBs, semiconductors, electronics, etc.

(The featured image of this article shows Dr. Wei-chung Lo delivering the opening remarks on the first day of IMPACT 2023. Dr. Lo is the Chair of IMPACT 2023, President of iMAPS – Taiwan, and Deputy Director of the Electronic and Optoelectronic System Research Laboratories at ITRI. Source: IMPACT.)

According to a report from Taiwan’s Commercial Times, industry experts assert that Silicon Photonics (SiPh) is poised to revolutionize the cloud industry as communication transmission speeds surge beyond 1.6 Tbps. Utilizing Co-Packaged Optics (CPO) for integration, SiPh combines optical components and Application-Specific Integrated Circuit (ASIC) technology into a singular module, effectively mitigating power consumption challenges.

Moreover, the versatility of SiPh is highlighted by its applications in communication transmission, biomedical sensing, LiDAR, high-speed AI transmission, smart healthcare, and autonomous vehicles, showcasing significant potential. This expansive range of potential applications underscores the promising future of SiPh technology.

Major players in the semiconductor landscape, including TSMC, ASE, SunSin, and Accton, express bullish sentiments towards SiPh and CPO technologies.

However, current hurdles such as chip yields and standardization remain, awaiting resolution. The anticipated timeline for tangible contributions is expected to extend beyond 2025.

In the realm of photonic integration, TSMC takes the lead among Taiwanese manufacturers. The company’s Compact Universal Photonics Engine (COUPE) offers heterogeneous integration of Photonic ICs (PICs) and Electronic ICs (EICs), resulting in a 40% reduction in energy consumption and a considerable increase in customer adoption likelihood.

TSMC has reportedly invested in a 200-person R&D team, collaborating with international clients for joint development.

ASE is actively involved in the research and development of SiPh and CPO packaging technology. Leveraging the VIPack advanced packaging platform, the market anticipates a gradual uptick in related businesses in the latter half of 2024, with significant order momentum expected to surge in 2025.

Networking company Accton is channeling efforts into the photonic integration of various components for switches. On the other hand, SunSin, a System-in-Package (SiP) testing and packaging facility, is strategically positioning itself in CPO process technology.

Explore more:

• What Is ‘Silicon Photonics’? Why Intel, TSMC, NVIDIA, Apple Are Investing
• Silicon Photonics Will Become Key to Semiconductor Future Development
• [News] TSMC Intensifies Silicon Photonics R&D, Rumored Collaboration with Broadcom and NVIDIA

(Image: ASE)

The AI landscape witnesses a robust surge with the consecutive launches of AMD’s “Instinct MI300” series AI chips and NVIDIA’s upcoming “B100” GPU structure. This wave of innovation propels a flourishing demand for AI-related Outsourced Semiconductor Assembly And Test Services (OSAT), surpassing initial estimates by over 10%. OSAT companies like ASE Holdings, King Yuan Electronics (KYEC), and Sigurd are poised to experience a notable uptick in revenue, as reported by UDN News.

According to reports, AMD is launching the “Instinct MI300” series AI chips this week, and NVIDIA plans to unveil the next-gen “B100” GPU next year. This successive release of new AI products by the two giants is boosting momentum in related OSATs collaboration.

NVIDIA is gearing up for the 2024 launch of its next-gen Blackwell architecture B100 GPU, saying AI performance exceeding twice that of the H200 GPU under the Hopper architecture, signifying a substantial leap in computational prowess.

Positive Outlook in 2024 for OSATs Amid AI Chip Development

Industry source indicates that due to the AI extensive computation requirements, advanced packaging is gradually becoming mainstream. This involves stacking chips and packaging them on a substrate. Depending on the arrangement, it is divided into 2.5D and 3D packaging. The advantage of this packaging technology is the ability to reduce chip space while also reducing power consumption and costs.

It is said the surge in AI chip orders from AMD and NVIDIA has led to a bottleneck in TSMC CoWoS advanced packaging capacity. This unexpected demand has exceeded projections for related OSATs, including ASE Holdings, KYEC, and Sigurd.

In the case of ASE Holdings, its subsidiary Siliconware Precision Industries (SPIL) possesses the advanced packaging capacity essential for generative AI chips. Joseph Tung, CFO of ASE Holdings, notes that while AI currently in its early-stage and is set to drive explosive growth. As AI integrates into existing and new applications, the demand for advanced packaging is expected to fuel the industry’s entry into the next super growth cycle.

For KYEC, a significant expansion in AI chip testing capacity since Q2 this year positions the company to benefit from the surge in demand.

Sigurd’s COO Tsan-Lien Yeh addresses that, with the release of AI phones, recognizing the doubled testing time for phone chips, which now carry APU/NPU for AI computing compared to general 5G chips. Sigurd has upgraded its equipment to align with future customer needs.

(Image: ASE VIPack’s video)

ASE Holdings conducted an earning conference on October 26th to unveil its Q3 financial results and offer insights into future business prospects. All eyes are on ASE’s progress in CoWoS advanced packaging. Joseph Tung, the Chief Financial Officer (CFO) of ASE, expressed confidence in AI and ongoing investments in advanced packaging, expecting a twofold increase in revenue share for advanced packaging in the coming year.

The market’s attention is keenly focused on wafer bank (a storage system used in semiconductor manufacturing to keep semiconductor wafers on hand for production, helping to streamline the manufacturing process) levels and inventory management. Tung mentioned that wafer bank levels are consistently declining and will further reduce Q4. With consumer electronics and computer clients gearing up to launch new products, inventory levels are expected to be maintained at a certain level. Overall, inventory reduction is nearing completion.

Tung emphasized that the real challenge lies not in inventory reduction but in the timing of the recovery in consumer demands and the impact of inflation. ASE remains cautious in its outlook for the upcoming year.

As for AI-related developments, Tung is optimistic about the expansion of CoWoS advanced packaging capacity through TSMC. ASE is also set to boost its production capacity for advanced packaging to cater to urgent customer demands. Next year, it is expected that revenue in advanced packaging will double. Tung emphasized that the AI era has already arrived and expects AI to extend to more terminal devices over the next few years. ASE has also invested in the development of Co-Packaged Optics (CPO) technology, ready to meet customer demands when the market is prepared.

To seize opportunities in advanced packaging, ASE previously introduced an Integrated Design Ecosystem (IDE) to optimize collaborative design tools through a platform, systematically enhancing advanced packaging architecture. This initiative has the potential to reduce design cycles by approximately 50%.

Tung pointed out that there are signs of a recovery in PC-related chip testing and packaging, and this year’s performance in automotive chip testing and packaging is expected to outperform other segments.

Looking ahead to future market conditions, Tung believes that the global semiconductor industry’s environment in the coming year will be more favorable than the current year.

(Image: ASE)

On October 11th, Amkor announced the official opening of its factory located in the Yen Phong 2C Industrial Park in Bac Ninh Province, Vietnam. The new facility, occupying 57 acres, is set to become Amkor’s largest, with an investment of approximately $1.6 billion by 2035. The factory primarily focuses on providing advanced system-level packaging and testing solutions to meet the semiconductor industry’s demand for advanced packaging. However, the company has not disclosed the factory’s current production and capacity.

Multiple Players Pursue CoWoS

The ongoing AI trend continues to drive demand for Chip-on-Wafer-on-Substrate (CoWoS) technology, benefiting TSMC, which holds a significant share of CoWoS production orders. However, companies like ASE Group, Amkor, and UMC are also positioning themselves in the CoWoS packaging manufacturing space. Industry experts believe that given the current high demand for TSMC’s CoWoS production, part of this demand may potentially shift to Amkor’s factories.

Furthermore, the popular Nvidia AI chips, which are in high demand globally, utilize 2.5D packaging technology, a responsibility currently held by TSMC. Recently, Nvidia hinted at the mass production of new AI chips like the GH200 and general server chip L40S, with reports suggesting that L40S will not require 2.5D packaging. Instead, it will be shared among several backend packaging companies, including ASE, Amkor, and SPIL.

Industry source has noted the strong demand for CoWoS in the AI sector, and with TSMC’s CoWoS production capacity already unable to meet demand for several quarters, some demand may potentially shift to Amkor or Samaung’s facilities.

Amkor has announced plans to expand its advanced packaging CoWoS-like capacity. According to industry insiders, Amkor’s monthly production capacity for 2.5D advanced packaging is expected to reach approximately 3,000 wafers in early 2023, with estimates of reaching 5,000 wafers by the end of 2023 and aiming for a significant increase to 7,000 units by the end of 2024.

Additionally, ASE Group has announced its presence in advanced CoWoS-related packaging. With their fan-out chip-on-substrate (FOCoS-Bridge) packaging technology, ASE has been chosen by major chip design house to handle their backend packaging after CoW.

In mid-September, South Korean media reported that Samsung is set to introduce its FO-PLP 2.5D advanced packaging technology to catch up with TSMC in the field of advanced packaging for AI chips. Samsung’s Advanced Packaging (AVP) team began developing FO-PLP advanced packaging for 2.5D chip packaging, allowing the integration of System-on-Chip (SoC) and High Bandwidth Memory (HBM) into an interposer to create a complete chip.

It’s worth mentioning that Samsung’s FO-PLP 2.5D packaging is rectangular, while TSMC’s CoWoS 2.5D uses a circular substrate. Samsung’s FO-PLP 2.5D packaging avoids edge substrate losses and boasts higher production efficiency. However, due to the need to transplant chips from wafers onto rectangular substrates, the process is more complex.

CoWoS Demand Continues

CoWoS technology is a form of 2.5D and 3D packaging, where chips are stacked and then packaged onto a substrate, resulting in a 2.5D or 3D structure. This technology reduces chip space, while also decreasing power consumption and costs. CoWoS packaging is applied in high-performance computing, artificial intelligence, data centers, 5G, the Internet of Things, automotive electronics, and other fields.

TrendForce research indicates a growing demand for advanced packaging technologies for AI and HPC chips. Currently, TSMC’s CoWoS is the primary choice for AI server chip production. CoWoS packaging mainly consists of CoW (Chip on Wafer), integrating various logic ICs (such as CPUs, GPUs, ASICs, etc.) and HBM memory, while oS (On Substrate) integrates CoW elements using Solder bump interconnects and packages them on a substrate. These CoWoS packages become the primary computing units on server motherboards, together with other components like networks, storage, power supply units (PSUs), and other I/O units, forming complete AI server systems.

Explore more

• Advanced Packaging in High Demand, TSMC and OAST Increasing Equipment Orders
• Understanding the 3D Packaging Trends Pursued by TSMC, Intel and Samsung
• An In-Depth Explanation of Advanced Packaging Technology: CoWoS

(Photo credit: Amkor)