The AI landscape witnesses a robust surge with the consecutive launches of AMD’s “Instinct MI300” series AI chips and NVIDIA’s upcoming “B100” GPU structure. This wave of innovation propels a flourishing demand for AI-related Outsourced Semiconductor Assembly And Test Services (OSAT), surpassing initial estimates by over 10%. OSAT companies like ASE Holdings, King Yuan Electronics (KYEC), and Sigurd are poised to experience a notable uptick in revenue, as reported by UDN News.

According to reports, AMD is launching the “Instinct MI300” series AI chips this week, and NVIDIA plans to unveil the next-gen “B100” GPU next year. This successive release of new AI products by the two giants is boosting momentum in related OSATs collaboration.

NVIDIA is gearing up for the 2024 launch of its next-gen Blackwell architecture B100 GPU, saying AI performance exceeding twice that of the H200 GPU under the Hopper architecture, signifying a substantial leap in computational prowess.

Positive Outlook in 2024 for OSATs Amid AI Chip Development

Industry source indicates that due to the AI extensive computation requirements, advanced packaging is gradually becoming mainstream. This involves stacking chips and packaging them on a substrate. Depending on the arrangement, it is divided into 2.5D and 3D packaging. The advantage of this packaging technology is the ability to reduce chip space while also reducing power consumption and costs.

It is said the surge in AI chip orders from AMD and NVIDIA has led to a bottleneck in TSMC CoWoS advanced packaging capacity. This unexpected demand has exceeded projections for related OSATs, including ASE Holdings, KYEC, and Sigurd.

In the case of ASE Holdings, its subsidiary Siliconware Precision Industries (SPIL) possesses the advanced packaging capacity essential for generative AI chips. Joseph Tung, CFO of ASE Holdings, notes that while AI currently in its early-stage and is set to drive explosive growth. As AI integrates into existing and new applications, the demand for advanced packaging is expected to fuel the industry’s entry into the next super growth cycle.

For KYEC, a significant expansion in AI chip testing capacity since Q2 this year positions the company to benefit from the surge in demand.

Sigurd’s COO Tsan-Lien Yeh addresses that, with the release of AI phones, recognizing the doubled testing time for phone chips, which now carry APU/NPU for AI computing compared to general 5G chips. Sigurd has upgraded its equipment to align with future customer needs.

(Image: ASE VIPack’s video)

ASE Holdings conducted an earning conference on October 26th to unveil its Q3 financial results and offer insights into future business prospects. All eyes are on ASE’s progress in CoWoS advanced packaging. Joseph Tung, the Chief Financial Officer (CFO) of ASE, expressed confidence in AI and ongoing investments in advanced packaging, expecting a twofold increase in revenue share for advanced packaging in the coming year.

The market’s attention is keenly focused on wafer bank (a storage system used in semiconductor manufacturing to keep semiconductor wafers on hand for production, helping to streamline the manufacturing process) levels and inventory management. Tung mentioned that wafer bank levels are consistently declining and will further reduce Q4. With consumer electronics and computer clients gearing up to launch new products, inventory levels are expected to be maintained at a certain level. Overall, inventory reduction is nearing completion.

Tung emphasized that the real challenge lies not in inventory reduction but in the timing of the recovery in consumer demands and the impact of inflation. ASE remains cautious in its outlook for the upcoming year.

As for AI-related developments, Tung is optimistic about the expansion of CoWoS advanced packaging capacity through TSMC. ASE is also set to boost its production capacity for advanced packaging to cater to urgent customer demands. Next year, it is expected that revenue in advanced packaging will double. Tung emphasized that the AI era has already arrived and expects AI to extend to more terminal devices over the next few years. ASE has also invested in the development of Co-Packaged Optics (CPO) technology, ready to meet customer demands when the market is prepared.

To seize opportunities in advanced packaging, ASE previously introduced an Integrated Design Ecosystem (IDE) to optimize collaborative design tools through a platform, systematically enhancing advanced packaging architecture. This initiative has the potential to reduce design cycles by approximately 50%.

Tung pointed out that there are signs of a recovery in PC-related chip testing and packaging, and this year’s performance in automotive chip testing and packaging is expected to outperform other segments.

Looking ahead to future market conditions, Tung believes that the global semiconductor industry’s environment in the coming year will be more favorable than the current year.

(Image: ASE)

On October 11th, Amkor announced the official opening of its factory located in the Yen Phong 2C Industrial Park in Bac Ninh Province, Vietnam. The new facility, occupying 57 acres, is set to become Amkor’s largest, with an investment of approximately $1.6 billion by 2035. The factory primarily focuses on providing advanced system-level packaging and testing solutions to meet the semiconductor industry’s demand for advanced packaging. However, the company has not disclosed the factory’s current production and capacity.

Multiple Players Pursue CoWoS

The ongoing AI trend continues to drive demand for Chip-on-Wafer-on-Substrate (CoWoS) technology, benefiting TSMC, which holds a significant share of CoWoS production orders. However, companies like ASE Group, Amkor, and UMC are also positioning themselves in the CoWoS packaging manufacturing space. Industry experts believe that given the current high demand for TSMC’s CoWoS production, part of this demand may potentially shift to Amkor’s factories.

Furthermore, the popular Nvidia AI chips, which are in high demand globally, utilize 2.5D packaging technology, a responsibility currently held by TSMC. Recently, Nvidia hinted at the mass production of new AI chips like the GH200 and general server chip L40S, with reports suggesting that L40S will not require 2.5D packaging. Instead, it will be shared among several backend packaging companies, including ASE, Amkor, and SPIL.

Industry source has noted the strong demand for CoWoS in the AI sector, and with TSMC’s CoWoS production capacity already unable to meet demand for several quarters, some demand may potentially shift to Amkor or Samaung’s facilities.

Amkor has announced plans to expand its advanced packaging CoWoS-like capacity. According to industry insiders, Amkor’s monthly production capacity for 2.5D advanced packaging is expected to reach approximately 3,000 wafers in early 2023, with estimates of reaching 5,000 wafers by the end of 2023 and aiming for a significant increase to 7,000 units by the end of 2024.

Additionally, ASE Group has announced its presence in advanced CoWoS-related packaging. With their fan-out chip-on-substrate (FOCoS-Bridge) packaging technology, ASE has been chosen by major chip design house to handle their backend packaging after CoW.

In mid-September, South Korean media reported that Samsung is set to introduce its FO-PLP 2.5D advanced packaging technology to catch up with TSMC in the field of advanced packaging for AI chips. Samsung’s Advanced Packaging (AVP) team began developing FO-PLP advanced packaging for 2.5D chip packaging, allowing the integration of System-on-Chip (SoC) and High Bandwidth Memory (HBM) into an interposer to create a complete chip.

It’s worth mentioning that Samsung’s FO-PLP 2.5D packaging is rectangular, while TSMC’s CoWoS 2.5D uses a circular substrate. Samsung’s FO-PLP 2.5D packaging avoids edge substrate losses and boasts higher production efficiency. However, due to the need to transplant chips from wafers onto rectangular substrates, the process is more complex.

CoWoS Demand Continues

CoWoS technology is a form of 2.5D and 3D packaging, where chips are stacked and then packaged onto a substrate, resulting in a 2.5D or 3D structure. This technology reduces chip space, while also decreasing power consumption and costs. CoWoS packaging is applied in high-performance computing, artificial intelligence, data centers, 5G, the Internet of Things, automotive electronics, and other fields.

TrendForce research indicates a growing demand for advanced packaging technologies for AI and HPC chips. Currently, TSMC’s CoWoS is the primary choice for AI server chip production. CoWoS packaging mainly consists of CoW (Chip on Wafer), integrating various logic ICs (such as CPUs, GPUs, ASICs, etc.) and HBM memory, while oS (On Substrate) integrates CoW elements using Solder bump interconnects and packages them on a substrate. These CoWoS packages become the primary computing units on server motherboards, together with other components like networks, storage, power supply units (PSUs), and other I/O units, forming complete AI server systems.

Explore more

• Advanced Packaging in High Demand, TSMC and OAST Increasing Equipment Orders
• Understanding the 3D Packaging Trends Pursued by TSMC, Intel and Samsung
• An In-Depth Explanation of Advanced Packaging Technology: CoWoS

(Photo credit: Amkor)

As AI demand continues to surge, TSMC (Taiwan Semiconductor Manufacturing Company) has initiated an extensive expansion plan for its CoWoS (Chip-on-Wafer-on-Substrate) production. Within the industry, reports suggest that TSMC, a leading semiconductor foundry, placed a significant wave of orders with Taiwanese equipment manufacturers last week, creating a notable impact.

Additionally, outsourced semiconductor assembly and testing (OSAT) giants, which were originally inquiring about orders, have also significantly increased their orders for advanced packaging. This wave of orders is estimated to be fulfilled between March and April of the upcoming year.

The growth in demand for advanced semiconductor processes due to AI applications necessitates advanced packaging technologies to keep pace. With packaging technologies advancing from 2D and 2.5D to the more advanced 3D IC (Integrated Circuit) configurations, the number of IC stacking layers is increasing, leading to a greater demand for advanced packaging equipment. Considering the current emphasis on CoWoS technology, the industry estimates that production capacity will reach 12,000 to 14,000 wafers in 2023 and double to over 30,000 wafers in 2024.

According to a report by Taiwan’s Money DJ, information from equipment industry sources reveals that TSMC recommenced orders for CoWoS equipment in April 2023, with a second wave of orders in June. Subsequently, sporadic additional orders were placed, and last week witnessed a new significant wave of orders, surprising many.

An anonymous executive from a Taiwanese equipment company expressed that they initially believed TSMC’s orders for CoWoS equipment had concluded, making the recent wave of orders even more unexpected. Furthermore, the increase in orders for advanced packaging equipment by semiconductor testing and packaging facilities is also seen as encouraging.

Market experts believe that semiconductor testing and packaging facilities and semiconductor foundries have different positions and advantages in the advanced packaging market. Their cooperative relationships outweigh their competition. Major OSAT players like ASE, Amkor, and JCET have long possessed advanced packaging technology and are positioned to become an alternative choice for major foundries due to their technical upgrades and competitive pricing. In other words, top-tier orders from customers will be firmly in TSMC’s grasp, while other opportunities will likely be pursued by SATS companies.

Regarding the supply of CoWoS equipment, suppliers like Scientech have received over 30 orders for wet etching processing equipment, while Grand Process Technology and others have shipped nearly 20 units. Meanwhile, G2C+ Alliance members such as GMM and C Sun have reportedly received over 40 orders from the TSMC’s Longtan factory.

(Photo credit: TSMC)

Advanced Semiconductor Engineering, Inc. (ASE) has unveiled its Integrated Design Ecosystem™ (IDE) – a collaborative design toolkit, meticulously tailored to enhance advanced package architecture on the VIPack™ platform. This innovation streamlines the transition from single-die SoC to multi-die disaggregated IP blocks, encompassing chiplets and memory integration through 2.5D or advanced fanout structures.

…