In-Depth Analyses
In response to the demands of high-performance computing, AI, 5G, and other applications, the shift towards chiplet and the incorporation of HBM memory has become inevitable for advanced chips. As a result, packaging has transitioned from 2D to 2.5D and 3D formats.
With chip manufacturing advancing towards more advanced process nodes, the model of directly packaging chips using advanced packaging technology from wafer foundries has emerged. However, this approach also signifies that wafer foundries will encroach upon certain aspects of traditional assembly and testing, leading to ongoing discussions about the ‘threat’ to traditional assembly and test firms since TSMC’s entry into advanced packaging in 2011.
But is this perspective accurate?
In fact, traditional assembly and test firms remain competitively positioned. Firstly, numerous electronic products still rely on their diverse traditional packaging techniques. Particularly, with the rapid growth of AIoT, electric vehicles, and drones, the required electronic components often still adopt traditional packaging methods. Secondly, faced with wafer foundries actively entering the advanced packaging domain, traditional assembly and test firms have not been idle, presenting concrete solutions to the challenge.
Advanced Packaging Innovations by Traditional Assembly and Test Firms
Since 2023, AI and AI server trends have rapidly emerged, driving the demand for AI chips. TSMC’s 2.5D advanced packaging technology, known as CoWoS, has played a pivotal role. However, the sudden surge in demand stretched TSMC’s capacity. In response, major traditional assembly and test firms such as ASE and Amkor have demonstrated their technical prowess and have no intention of being absent from this field.
For instance, ASE’s FOCoS technology enables the integration of HBM and ASIC. It restructures multiple chips into a fan-out module, which is then placed on the substrate, achieving the integration of multiple chips. Their FOCoS-Bridge technology, unveiled in May this year, utilizes silicon bridges (Si Bridge) to accomplish 2.5D packaging, bolstering the creation of advanced chips required for applications like AI, data centers, and servers.
Additionally, SPIL, a subsidiary of ASE, offers the FO-EB technology, a powerful integration of logic IC and HBM. As depicted below, this technology eschews silicon interposers, utilizing silicon bridges and redistribution layers (RDL) for connections, similarly capable of 2.5D packaging.
Another major player, Amkor, has not only collaborated with Samsung to develop the H-Cube advanced packaging solution but has also long been involved in ‘CoWoS-like technology.’ Through intermediary layers and through-silicon via (TSV) technology, Amkor can interconnect different chips, also possessing 2.5D advanced packaging capabilities.
China’s major assembly and test firm, Jiangsu Changjiang Electronics Technology (JCET), employs the XDFOI technology, integrating logic ICs with HBM through TSV, RDL, and microbump techniques, aimed at high-performance computing.
Given the recent surge in demand for high-end GPU chips, TSMC’s CoWoS capacity has fallen short, and NVIDIA is actively seeking support from second or even third suppliers. The ASE Group and Amkor have secured partial orders through their packaging technologies. This clearly illustrates that traditional assembly and test firms, even when faced with the entry of wafer foundries into the advanced packaging domain, still possess the capability to compete.
In terms of product types, wafer foundries focus on advanced packaging technology for major players like NVIDIA and AMD. Meanwhile, other products not in the highest-end category still opt for traditional assembly and test firms like ASE, Amkor, and JCET for manufacturing. Overall, with their presence in advanced packaging, as well as a hold on the expanding existing packaging market, traditional assembly and test firms continue to maintain their market competitiveness.
(Photo credit: Amkor)
In-Depth Analyses
The surge in AIGC and new technologies such IoT, AI, 5G, AR/VR are driving a huge demand for computational power of high-end chips. This has been even outpacing the performance increase offered by the long-standing Moore’s Law, ushering in a “post-Moore” era where revolutions in advanced chip design are crucial.
Over recent years, chiplet design has seemingly become the mainstream approach for upgrading high-end chips. The concept is to allow more transistors on a single chip, effectively increasing the production yield of high-end chips while reducing overall costs.
By the large, major IC players have all jumped on board. Even Apple has joined the game by releasing their M1 Ultra SoC using the chiplet concept, which doubles computational performance by integrating two M1 Max units in a single chip.
The CPU sector is definitely a clear demonstration of this trend:
Transition from Bumping to Hybrid Bonding
Our analysis in “Chiplet Design: A Real Game-Changer for Substrates” laid out the comprehensive impact of the evolution of chiplet technology on substrates. In fact, chiplets have already caused a significant disruption to the most advanced semiconductor packaging technologies, necessitating the transition towards advanced 2.5D and 3D packaging technologies.
The bottleneck of advanced packaging lies in the chiplets’ interconnections, with bump and microbump still being the key technology for linking chips and forming I/O joints. These connection densities are hard to enhance, thus limiting the overall chip’s transmission speed. In addition, the more chiplets being stacked, the bigger the chip volume gets. The challenge is how to limit the chip size within a specific range, considering the current technical constraints.
Therefore, copper-to-copper hybrid bonding, also known as DBI (Direct Bond Interconnect), has been emerging as the key technology route that overcomes major hurdles in chiplet integration from the bottom-up.
Unlike bumping technology, hybrid bonding significantly shrinks the I/O joint space. The future transmission demand requires the I/O joint space between chiplets to be less than 10µm. While bumping is limited to around 20µm, hybrid bonding can take this down to an impressive 1µm or even less. This also means more I/O joints can be fitted in the same chip size – even reaching up to millions on a mere 1cm2 chip.
On top of this, hybrid bonding only adds an extra 1-2µm of thickness, compared to the 10-30µm of microbump, thereby helping reduce the thickness of stacked chips.
To put it simply, hybrid bonding can boost transmission efficiency, minimize energy usage with higher density of copper joints, manage chip volume, and even cut down on material costs.
The Race for Advanced Packaging Is Kicking Off
Moving forward, hybrid bonding is set to become the key technology supporting the continuous development of chiplet design and 3D packaging. This has been exemplified by TSMC’s front-end So IC packaging technology which is based on hybrid bonding. This puts AMD, a key customer of TSMC, in a favorable position to get ahead.
From AMD’s roadmap of 3D V-Cache technology, they have stacked SRAM on top of CCX (CPU Complex), and gradually integrated it into Milan-X series, the EPYC server CPUs, and Ryzen series, the consumer-grade CPUs, over the past two years. This has significantly improved performance and power consumption as a whole.
Not to be outdone, this year Intel also launched their Foveros Direct packaging technology, which is also based on hybrid bonding route. Assuming everything proceeds smoothly, we can anticipate the release of CPUs utilizing Foveros Direct technology by 2024.
As we look at the current products, AMD’s hybrid bonding apparently focuses on stacking SRAM and computing units at the moment. However, as CPU leaders deepen their understanding of this technology, the application field is expected to further expand. In other words, the future of hybrid bonding solutions stacking multiple computation units is just around the corner.
Insights
In the post-Moore’s Law era, chiplet design has been burgeoning as the mainstream architecture.
With the widespread adoption of EUV technology by foundries on process nodes of 5nm and below, the cost of semiconductor fabrication has skyrocketed. The cost of the 5nm process has grown by almost 1x compared to the 7nm process, and the 3nm process is expected to increase by almost 1x compared to the 5nm process.
To address this issue, IC design companies have started to split chip components or connect multiple chips and adopt advanced packaging such as 2.5D/3D IC to integrate multiple chips together.
Compared to traditional chip design methods, chiplet design has superior characteristics such as shorter upgrade cycles, lower costs, and higher yields, which is one of the reasons why chiplet technology is gaining popularity.
AMD’s chiplet design is a representative example. Through close collaboration with TSMC, AMD has fully transitioned its CPUs to chiplets since the 7nm process, with the Ryzen 7000 series CPU and Radeon RX 7000 series graphics cards released in 2022. The latter uses the RDNA 3 architecture and integrates the GCD and MCD produced by the 5nm and 6nm processes respectively, as a result improving overall performance, with a 54% increase in RDNA 3’s Performance per Watt.
Under the leadership of industry leaders such as AMD and Intel, chiplet design has had a significant impact on the entire semiconductor industry – substrates manufacturers in particular.
ABF Substrates Set to Soar
Aside from CPUs, developments in AMD and Intel’s server platforms indicate that the trend towards higher-layer-count and larger-area ABF substrates is expected to continue.
Given the server shipment volume is expected to remain stable and grow steadily in the mid to low single digits for the next 3-5 years, the growth momentum of ABF substrates mainly comes from the increase in layer count and area brought by 2.5D/3D packaging adoption in servers.
Starting in 2020, ABF substrates saw a surge in demand due to the pandemic. The supply-demand gap peaked in 2021, and in the first half of 2022, ABF substrate prices increased while volume increased and gross profit margins hit new highs.
Due to the impact of shortage in ABF substrates in 2020-2021, major substrate manufacturers have initiated large-scale expansion plans, with the expectation that demand for ABF substrates would continue to grow with the upcoming releases of new server platforms and the integration of 2.5D packaging for PC CPUs.
Growing demands with Some Hiccups
However, the moves have been put on hold for now. Since the second half of 2022, due to inventory correction in the overall semiconductor industry and the delayed production time of Intel’s new server platform, there’s been a supply glut in ABF substrates.
Therefore, Unimicron has taken the lead in adjusting its capital expenditure plans, reducing its planned capacity increase for 2023 from about 20% to only 3.5%. AT&S has also tentatively postponed the significant increase in capacity planned for the end of 2024. It is unclear when the expansion will resume or whether the expansion will be scaled back.
This indicates that current substrate manufacturers have not only lowered their demand projections for 2023, but also for 2025-2026. Further adjustments to the expansion plans of other manufacturers will also affect the future market supply-demands dynamics.
Back on Track for Major Growth in 2024
Looking into the future, things are looking up for the ABF substrate industry. In the second quarter of 2023, we can expect the release of new server platforms from AMD and Intel, as well as the completion of PC inventory adjustments.
With expansion plans in place, it’s predicted that global ABF substrate production capacity will only increase by 15-20% in the latter half of 2023, continuing to put pressure on substrate manufacturers, according to TrendForce.
Things are expected to pick up in 2024 with the release of AMD and Intel’s next-generation server platforms, Zen 5 and Birch Stream. Plus, the anticipated introduction of 2.5D packaging for PC CPUs will drive a new wave of demand for ABF substrates. All in all, we can expect a significant rebound for the ABF substrate industry in 2024.