The surge in demand for advanced packaging is being primarily propelled by artificial intelligence (AI) chips. According to industry sources cited by CNA, TSMC’s CoWoS production capacity is set to double this year, yet demand continues to outstrip supply. In response, NVIDIA has enlisted the help of packaging and testing facilities to augment its advanced packaging capabilities.

In addition, to address the imbalance between supply and demand for advanced packaging due to AI, semiconductor backend specialty assembly and testing (OSAT) companies such as ASE Technology Holding (ASE), Powertech Technology, and KYEC have expanded their capital expenditures this year to enhance their advanced packaging capabilities, aligning with the needs of their customers.

AI and high-performance computing (HPC) chips are driving the demand for CoWoS advanced packaging. As per sources interviewed by CNA, from July to the end of last year, TSMC actively adjusted its CoWoS advanced packaging production capacity, gradually expanding and stabilizing mass production.

The source further indicates that in December of last year, TSMC’s CoWoS monthly production capacity increased to 14,000 to 15,000. It is estimated that by the fourth quarter of this year, TSMC’s CoWoS monthly production capacity will significantly expand to 33,000 to 35,000.

Per an earlier report from Commercial Times, TSMC has been outsourcing part of its CoWoS operations for some time, mainly targeting small-volume, high-performance chips. TSMC maintains in-house production of the CoW, while the back-end WoS is handed over to test and assembly houses to improve production efficiency and flexibility. 

However, the demand for advanced packaging capacity for AI chips still outstrips supply. Sources cited by CNA also reveal that NVIDIA has sought assistance from packaging and testing subcontractors outside of TSMC to augment their advanced packaging capabilities.

Amkor, among others, began gradually providing capacity support from the fourth quarter of last year, while SPIL, a subsidiary of ASE, is slated to commence supply in the first quarter of this year.

Read more

• [News] AMD Eyes CoWoS-like Supply for AI Chips with TSMC Full Capacity
• [News] CoWoS Capacity Shortage Challenges AI Chip Demand, while Taiwanese Manufacturers Expand to Seize Opportunities

(Photo credit: TSMC)

With the flourishing development of technologies such as AI, cloud computing, big data analytics, and mobile computing, modern society has an increasingly high demand for computing power.

Moreover, with the advancement beyond 3 nanometers, wafer sizes have encountered scaling limitations and manufacturing costs have increased. Therefore, besides continuing to develop advanced processes, the semiconductor industry is also exploring other ways to maintain chip size while ensuring high efficiency.

The concept of “heterogeneous integration” has become a contemporary focus, leading to the transition of chips from single-layer to advanced packaging with multiple layers stacked together.

The term “CoWoS” can be broken down into the following definitions: “Cow” stands for “Chip-on-Wafer,” referring to the stacking of chips, while “WoS” stands for “Wafer-on-Substrate,” which involves stacking chips on a substrate.

Therefore, “CoWoS” collectively refers to stacking chips and packaging them onto a substrate. This approach reduces the space required for chips and offers benefits in reducing power consumption and costs.

Among these, CoWoS can be further divided into 2.5D horizontal stacking (most famously exemplified by TSMC’s CoWoS) and 3D vertical stacking versions. In these configurations, various processor and memory modules are stacked layer by layer to create chiplets. Because its primary application lies in advanced processes, it is also referred to as advanced packaging.

According to TrendForce’s data, it has provided insights into the heat of the AI chip market. In 2023, shipments of AI servers (including those equipped with GPU, FPGA, ASIC, etc.) reached nearly 1.2 million units, a 38.4% increase from 2022, accounting for nearly 9% of the overall server shipments.

Looking ahead to 2026, the proportion is expected to reach 15%, with a compound annual growth rate (CAGR) of AI server shipments from 2022 to 2026 reaching 22%.

Due to the advanced packaging requirements of AI chips, TSMC’s 2.5D advanced packaging CoWoS technology is currently the primary technology used for AI chips.

GPUs, in particular, utilize higher specifications of HBM, which require the integration of core dies using 2.5D advanced packaging technology. The initial stage of chip stacking in CoWoS packaging, known as Chip on Wafer (CoW), primarily undergoes manufacturing at the fab using a 65-nanometer process. Following this, through-silicon via (TSV) is carried out, and the finalized products are stacked and packaged onto the substrate, known as Wafer on Substrate (WoS).

As a result, the production capacity of CoWoS packaging technology has become a significant bottleneck in AI chip output over the past year, and it remains a key factor in whether AI chip demand can be met in 2024. Foreign analysts have previously pointed out that NVIDIA is currently the largest customer of TSMC’s 2.5D advanced packaging CoWoS technology.

This includes NVIDIA’s H100 GPU, which utilizes TSMC’s 4-nanometer advanced process, as well as the A100 GPU, which uses TSMC’s 7-nanometer process, both of which are packaged using CoWoS technology. As a result, NVIDIA’s chips account for 40% to 50% of TSMC’s CoWoS packaging capacity. This is also why the high demand for NVIDIA chips has led to tight capacity for TSMC’s CoWoS packaging.

TSMC’s Expansion Plans Expected to Ease Tight Supply Situation in 2024

During the earnings call held in July 2023, TSMC announced its plans to double the CoWoS capacity, indicating that the supply-demand imbalance in the market could be alleviated by the end of 2024.

Subsequently, in late July 2023, TSMC announced an investment of nearly NTD 90 billion (roughly USD 2.87 billion) to establish an advanced packaging fab in the Tongluo Science Park, with the construction expected to be completed by the end of 2026 and mass production scheduled for the second or third quarter of 2027.

In addition, during the earnings call on January 18, 2024, TSMC’s CFO, Wendell Huang, emphasized that TSMC would continue its expansion of advanced processes in 2024. Therefore, it is estimated that 10% of the total capital expenditure for the year will be allocated towards expanding capacity in advanced packaging, testing, photomasks, and other areas.

In fact, NVIDIA’s CFO, Colette Kress, stated during an investor conference that the key process of CoWoS advanced packaging has been developed and certified with other suppliers. Kress further anticipated that supply would gradually increase over the coming quarters.

Regarding this, J.P. Morgan, an investment firm, pointed out that the bottleneck in CoWoS capacity is primarily due to the supply-demand gap in the interposer. This is because the TSV process is complex, and expanding capacity requires more high-precision equipment. However, the long lead time for high-precision equipment, coupled with the need for regular cleaning and inspection of existing equipment, has resulted in supply shortages.

Apart from TSMC’s dominance in the CoWoS advanced packaging market, other Taiwanese companies such as UMC, ASE Technology Holding, and Powertek Technology are also gradually entering the CoWoS advanced packaging market.

Among them, UMC expressed during an investor conference in late July 2023 that it is accelerating the deployment of silicon interposer technology and capacity to meet customer needs in the 2.5D advanced packaging sector.

UMC Expands Interposer Capacity; ASE Pushes Forward with VIPack Advanced Packaging Platform

UMC emphasizes that it is the world’s first foundry to offer an open system solution for silicon interposer manufacturing. Through this open system collaboration (UMC+OSAT), UMC can provide a fully validated supply chain for rapid mass production implementation.

On the other hand, in terms of shipment volume, ASE Group currently holds approximately a 32% market share in the global Outsourced Semiconductor Assembly and Test (OSAT) industry and accounts for over 50% of the OSAT shipment volume in Taiwan. Its subsidiary, ASE Semiconductor, also notes the recent focus on CoWoS packaging technology. ASE Group has been strategically positioning itself in advanced packaging, working closely with TSMC as a key partner.

ASE underscores the significance of its VIPack advanced packaging platform, designed to provide vertical interconnect integration solutions. VIPack represents the next generation of 3D heterogeneous integration architecture.

Leveraging advanced redistribution layer (RDL) processes, embedded integration, and 2.5D/3D packaging technologies, VIPack enables customers to integrate multiple chips into a single package, unlocking unprecedented innovation in various applications.

Powertech Technology Seeks Collaboration with Foundries; Winbond Electronics Offers Heterogeneous Integration Packaging Technology

In addition, the OSAT player Powertech Technology is actively expanding its presence in advanced packaging for logic chips and AI applications.

The collaboration between Powertech and Winbond is expected to offer customers various options for CoWoS advanced packaging, indicating that CoWoS-related advanced packaging products could be available as early as the second half of 2024.

Winbond Electronics emphasizes that the collaboration project will involve Winbond Electronics providing CUBE (Customized Ultra-High Bandwidth Element) DRAM, as well as customized silicon interposers and integrated decoupling capacitors, among other advanced technologies. These will be complemented by Powertech Technology’s 2.5D and 3D packaging services.

Read more

• [News] AMD Eyes CoWoS-like Supply for AI Chips with TSMC Full Capacity
• [News] Samsung Boosts 2.5D Packaging Equipment to Compete for TSMC’s CoWoS Orders

(Photo credit: TSMC)

Apple’s product line is rumored to set for a significant upgrade. According to a report from Economic Daily News, the next-generation M4 and A18 processors, slated for iPads, MacBooks, and iPhones, are expected to increase the number of built-in AI computing cores, leading to a substantial growth in orders to TSMC. Consequently, TSMC’s production volume for its enhanced 3-nanometer process this year is forecasted to surge by over 50% compared to last year.

As per a report cited by the Economic Daily News, Apple, recognizing the significant AI trend, is not only significantly enhancing the AI computing power of the M3 and A17 processors this year, but also increasing the number and efficiency of AI computing cores in the next-generation M4 and A18 processors. The AI application adoption rate across all product lines is expected to greatly increase.

Apple is strengthening the AI computing performance of its terminal devices and significantly increasing the computational power of its in-house processors, resulting in a simultaneous substantial increase in orders to TSMC.

The report further cited sources indicating that Apple’s orders for TSMC’s enhanced 3nm process this year are rumored to increase by over 50% compared to last year, solidifying its position as TSMC’s largest customer.

In addition to increasing orders for TSMC’s wafer production, reportedly, Apple has also secured a significant amount of advanced packaging capacity from TSMC. Industry sources cited by the Economic Daily News has indicated that Apple primarily places orders with TSMC for advanced packaging processes such as InFO and CoWoS, which are 2.5D advanced packaging technologies.

This year, there is a possibility that Apple will push its advanced packaging requirements to the highest price and difficulty level, such as the 3D structure SoIC advanced packaging.

TSMC, reportedly, is expanding its production capacity for the 3nm family and advanced packaging this year to meet the large orders from major clients such as Apple, NVIDIA, and AMD in the coming years.

As per TrendForce’s data, the 3nm process alone contributed 6% to TSMC’s Q3 revenue, with advanced processes (≤7nm) accounting for nearly 60% of its total revenue.

TSMC had previously announced during its earnings call that its capital budget for this year is expected to fall between USD 28 billion to USD 32 billion, with 70% to 80% allocated for advanced processes, 10% to 20% for specialty processes, and the remaining 10% for advanced packaging, testing, and mask production.

Read more

• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC
• [News] TSMC’s Primary Client for 2nm Chips Expected to be Apple, Set to Debut with iPhone 17 Lineup Next Year

(Photo credit: TSMC)

In the surge of AI advancements, a CoWoS expansion wave is rapidly underway, with TSMC showcasing ongoing ambitions in advanced packaging.

According to MoneyDJ, recent industry reports suggest that TSMC is revising upward its capacity plans for SoIC (System-on-Integrated-Chips). By the end of this year, monthly production capacity is expected to jump from around 2,000 units in late 2023 to 5,000-6,000 units, addressing robust demand in the future for AI and HPC.

TSMC’s SoIC represents an industry-first high-density 3D chip stacking technology. Through the Chip on Wafer (CoW) packaging technique, it enables heterogeneous integration of chips with different sizes, functions, and nodes. Production has commenced at its advanced backend Fab 6 in Zhunan.

Quoting industry sources, MoneyDJ reports that SoIC’s monthly capacity was initially set to expand to 3,000-4,000 units this year from 2,000 units at the end of last year. However, it is now revised upward to 5,000-6,000 units, with a goal to double the capacity by 2025.

CoWoS, a mature technology with 15 years of development, is estimated to reach a monthly capacity of 30,000-34,000 units by the end of this year. TSMC is banking on its globally dominant 3D stacking technology with SoIC. The debut of major customer AMD MI300 utilizing SoIC with CoWoS is seen as pivotal. If successful, AMD could dominate the AI server sector, making TSMC’s SoIC a significant achievement.

Furthermore, Apple, TSMC’s largest customer, is reportedly keenly interested in SoIC. It is said to adopt SoIC with Hybrid Molding technology, currently in small-scale trial production and expected to enter mass production in 2025-2026. The plan is to apply it in products like Mac and iPad, offering cost advantages over current solutions.

As for another major customer of TSMC’s advanced packaging, NVIDIA, although high-end products currently favor CoWoS packaging, the industry anticipates the future integration of SoIC technology.

(Image: TSMC)

TSMC operates at full capacity, AMD aims for AI chips reportedly seeks CoWoS-like supply chain.

In 2023, NVIDIA led the global AI chip development, and in 2024, the global demand for AI chips is expected to continue to surge due to the expansion of end-user applications such as PCs and mobile phones.

Meanwhile, AMD has not stopped in AI chip development either, with the expected MI300 products poised to heat up the global AI business opportunities. However, the key to supply lies in advanced packaging, and AMD will seek outsourced semiconductor assembly and test (OSAT) service providers to offer support similar to CoWoS.

According to Taiwan’s Commercial Times, TSMC’s CoWoS capacity has long been fully loaded, and even if it expands production this year, it will mainly be reserved for NVIDIA. Market sources pointed out that TSMC will continue to increase CoWoS capacity to support AMD’s demand, but it takes six to nine months to establish a new production line. Therefore, it is expected that AMD will seek cooperation with other companies with CoWoS-like packaging capabilities. ASE, Amkor, Powertech, and KYEC are the first batch of potential partners.

TSMC has been outsourcing part of its CoWoS operations for some time, mainly targeting small-volume, high-performance chips. TSMC maintains in-house production of the CoW, while the back-end WoS is handed over to test and assembly houses to improve production efficiency and flexibility. This model will continue in the future 3D IC generation.

ASE and Amkor both received WoS orders last year. ASE has strengthened the development of advanced packaging technology and has a complete solution for the entire CoWoS process. ASE previously stated that it sees the strong potential of AI and expects related revenue to double in 2024.

According to reports citing market sources, the monthly production capacity of the ASE Group’s 2.5D packaging is about 2,000 to 2,500 pieces. Some experts believe that test and assembly houses will maintain the business model of TSMC or UMC providing the interposer. Therefore, in 2024, a significant increase in CoWoS production capacity is expected.

KYEC is responsible for testing Nvidia AI chips and is expected to benefit from AMD’s search for CoWoS-like capacity. Nvidia is currently KYEC’s second-largest customer.

KYEC’s testing of Nvidia A100 and H100 chips is mainly in the final test (FT), with a market share of up to 70%. KYEC provides comprehensive IC burn-in testing, has self-developed burn-in equipment, and has been in the industry for more than a decade, accumulating many patents and technologies.

AMD stated at the end of 2023 that AI chip revenue could reach US$2 billion in 2024, excluding other HPC chips. AMD pointed out that the annual compound growth rate of the AI chip market in the next four years will reach 70%, and it is estimated that it will reach US$400 billion in 2027.

(Image: AMD)