According to the news from Liberty Times Net, NVIDIA’s Q2 financials and Q3 forecasts have astounded the market, driven by substantial growth in their AI-centric data center operations. NVIDIA addresses CoWoS packaging supply issues by collaborating with other suppliers, boosting future capacity, and meeting demand. This move is echoed in South Korea’s pursuit of advanced packaging strategies.

South Korea’s Swift Pursuit on Advanced Packaging

The semiconductor industry highlights that the rapid development of generative AI has outpaced expectations, causing a shortage of advanced packaging production capacity. Faced with this supply-demand gap, TSMC has outsourced some of its capacity, with Silicon Interposer production being shared by facilities under the United Microelectronics Corporation and Siliconware Precision Industries. UMC has also strategically partnered with Siliconware Precision Industries, and Amkor’s Korean facilities have joined the ranks of suppliers to augment production capacity.

Due to equipment limitations, TSMC’s monthly CoWoS advanced packaging capacity is expected to increase from 10,000 units to a maximum of 12,000 units by the end of this year. Meanwhile, other suppliers could potentially raise their CoWoS monthly capacity to 3,000 units. TSMC aims to boost its capacity to 25,000 units by the end of next year, while other suppliers might elevate theirs to 5,000 units.

According to the source South Korean media, Samsung entered the scene, competing for advanced packaging orders against NVIDIA. South Korea initiated a strategic research project to rapidly narrow the gap in packaging technology within 5~7 years, targeting giants like TSMC, Amkor, and China’s JCET.

(Source: https://ec.ltn.com.tw/article/paper/1601162)

According to a report from Taiwan’s Commercial Times, NVIDIA is aggressively establishing a non-TSMC CoWoS supply chain. Sources in the supply chain reveal that UMC is proactively expanding silicon interposer capacity, doubling it in advance, and now planning to further increase production by over two times. The monthly capacity for silicon interposers will surge from the current 3 kwpm (thousand wafers per month) to 10 kwpm, potentially aligning its capacity with TSMC’s next year, significantly alleviating the supply strain in the CoWoS process.

A prior report from Nomura Securities highlighted NVIDIA’s efforts since the end of Q2 this year to construct a non-TSMC supply chain. Key players include UMC for wafer fabrication, Amkor and SPIL for packaging and testing. NVIDIA aims to add suppliers to meet the surging demand for CoWoS solutions.

The pivotal challenge in expanding CoWoS production lies in insufficient silicon interposer supply. In the future, UMC will provide the silicon interposers for front-end CoW process, while Amkor and SPLI will take charge of the back-end WoS packaging. These collaborations will establish a non-TSMC CoWoS supply chain.

UMC states its current silicon interposer capacity stands at 3 kwpm. However, the company has decided to undertake a one-fold expansion at its Singaporean plant, targeting a capacity of around 6 kwpm. The additional capacity is anticipated to be progressively operational within 6 to 9 months, with the earliest projections for the first quarter of next year.

Yet, due to persistent robust market demand, it’s expected that even with UMC’s capacity expansion to 6 kwpm, it may not completely meet market needs. Consequently, industry sources suggest UMC has opted to further amplify silicon interposer capacity to 10 kwpm, aiming for a two-fold acceleration of production expansion. Addressing these expansion rumors, UMC affirms that growth in advanced packaging demand is an inherent trend and future focus, asserting their evaluation of capacity options and not ruling out the possibility of continuous enlargement of silicon interposer capabilities.

(Photo credit: Amkor)

According to the Korea Economic Daily. Samsung Electronics’ HBM3 and packaging services have passed AMD’s quality tests. The upcoming Instinct MI300 series AI chips from AMD are planned to incorporate Samsung’s HBM3 and packaging services. These chips, which combine central processing units (CPUs), graphics processing units (GPUs), and HBM3, are expected to be released in the fourth quarter of this year.

Samsung is noted as the sole provider capable of offering advanced packaging solutions and HBM products simultaneously. Originally considering TSMC’s advanced packaging services, AMD had to alter its plans due to capacity constraints.

The surge in demand for high-performance GPUs within the AI landscape benefits not only GPU manufacturers like NVIDIA and AMD, but also propels the development of HBM and advanced packaging.

In the backdrop of the AI trend, AIGC model training and inference require the deployment of AI servers. These servers typically require mid-to-high-end GPUs, with HBM penetration nearing 100% among these GPUs.

Presently, Samsung, SK Hynix, and Micron are the primary HBM manufacturers. According to the latest research by TrendForce, driven by the expansion efforts of these original manufacturers, the estimated annual growth rate of HBM supply in 2024 is projected to reach 105%.

In terms of competitive dynamics, SK Hynix leads with its HBM3 products, serving as the primary supplier for NVIDIA’s Server GPUs. Samsung, on the other hand, focuses on fulfilling orders from other cloud service providers. With added orders from customers, the gap in market share between Samsung and SK Hynix is expected to narrow significantly this year. The estimated HBM market share for both companies is about 95% for 2023 to 2024. However, variations in customer composition might lead to sequential variations in bit shipments.

In the realm of advanced packaging capacity, TSMC’s CoWoS packaging technology dominates as the main choice for AI server chip suppliers. Amidst strong demand for high-end AI chips and HBM, TrendForce estimates that TSMC’s CoWoS monthly capacity could reach 12K by the end of 2023.

With strong demand driven by NVIDIA’s A100 and H100 AI Server requirements, demand for CoWoS capacity is expected to rise by nearly 50% compared to the beginning of the year. Coupled with the growth in high-end AI chip demand from companies like AMD and Google, the latter half of the year could experience tighter CoWoS capacity. This robust demand is expected to continue into 2024, potentially leading to a 30-40% increase in advanced packaging capacity, contingent on equipment readiness.

(Photo credit: Samsung)

In response to the demands of high-performance computing, AI, 5G, and other applications, the shift towards chiplet and the incorporation of HBM memory has become inevitable for advanced chips. As a result, packaging has transitioned from 2D to 2.5D and 3D formats.

With chip manufacturing advancing towards more advanced process nodes, the model of directly packaging chips using advanced packaging technology from wafer foundries has emerged. However, this approach also signifies that wafer foundries will encroach upon certain aspects of traditional assembly and testing, leading to ongoing discussions about the ‘threat’ to traditional assembly and test firms since TSMC’s entry into advanced packaging in 2011.

But is this perspective accurate?

In fact, traditional assembly and test firms remain competitively positioned. Firstly, numerous electronic products still rely on their diverse traditional packaging techniques. Particularly, with the rapid growth of AIoT, electric vehicles, and drones, the required electronic components often still adopt traditional packaging methods. Secondly, faced with wafer foundries actively entering the advanced packaging domain, traditional assembly and test firms have not been idle, presenting concrete solutions to the challenge.

Advanced Packaging Innovations by Traditional Assembly and Test Firms

Since 2023, AI and AI server trends have rapidly emerged, driving the demand for AI chips. TSMC’s 2.5D advanced packaging technology, known as CoWoS, has played a pivotal role. However, the sudden surge in demand stretched TSMC’s capacity. In response, major traditional assembly and test firms such as ASE and Amkor have demonstrated their technical prowess and have no intention of being absent from this field.

For instance, ASE’s FOCoS technology enables the integration of HBM and ASIC. It restructures multiple chips into a fan-out module, which is then placed on the substrate, achieving the integration of multiple chips. Their FOCoS-Bridge technology, unveiled in May this year, utilizes silicon bridges (Si Bridge) to accomplish 2.5D packaging, bolstering the creation of advanced chips required for applications like AI, data centers, and servers.

Additionally, SPIL, a subsidiary of ASE, offers the FO-EB technology, a powerful integration of logic IC and HBM. As depicted below, this technology eschews silicon interposers, utilizing silicon bridges and redistribution layers (RDL) for connections, similarly capable of 2.5D packaging.

Another major player, Amkor, has not only collaborated with Samsung to develop the H-Cube advanced packaging solution but has also long been involved in ‘CoWoS-like technology.’ Through intermediary layers and through-silicon via (TSV) technology, Amkor can interconnect different chips, also possessing 2.5D advanced packaging capabilities.

China’s major assembly and test firm, Jiangsu Changjiang Electronics Technology (JCET), employs the XDFOI technology, integrating logic ICs with HBM through TSV, RDL, and microbump techniques, aimed at high-performance computing.

Given the recent surge in demand for high-end GPU chips, TSMC’s CoWoS capacity has fallen short, and NVIDIA is actively seeking support from second or even third suppliers. The ASE Group and Amkor have secured partial orders through their packaging technologies. This clearly illustrates that traditional assembly and test firms, even when faced with the entry of wafer foundries into the advanced packaging domain, still possess the capability to compete.

In terms of product types, wafer foundries focus on advanced packaging technology for major players like NVIDIA and AMD. Meanwhile, other products not in the highest-end category still opt for traditional assembly and test firms like ASE, Amkor, and JCET for manufacturing. Overall, with their presence in advanced packaging, as well as a hold on the expanding existing packaging market, traditional assembly and test firms continue to maintain their market competitiveness.

(Photo credit: Amkor)

According to Taiwan’s Commercial Times, TSMC continues to face challenges from ongoing price undercutting and competitive bidding in mature semiconductor manufacturing processes. Concerns arise about the company’s ability to offset these challenges with AI-related orders. Reports from the market suggest that on July 20th, TSMC revised down its fiscal forecast for the year for the second time, slashing its annual revenue target (in USD) from an anticipated decline of 1% to 6% to a significant reduction of 10%. However, given the persistent sluggish economic conditions of late, there is speculation of a potential third adjustment that could lead to a year-on-year revenue decline of 12%.

In the current investment landscape, artificial intelligence has become a focal point this year. Additionally, the strong demand for CoWoS packaging has contributed to a positive outlook for TSMC. However, it’s important to note that AI’s contribution to TSMC’s overall revenue is not substantial.

Using the popular H100 model from NVIDIA as an example, it only impacts TSMC’s performance in the N4 manufacturing process. This limited contribution falls short of countering the downward trend in consumer product demand utilizing the N3 and N7 manufacturing processes.

Market Speculations Emerge About TSMC’s Performance and Challenges

Market sources indicate that TSMC’s performance in mature processes (7nm and above) accounted for 47% of its output in the second quarter. While prices managed to hold steady in the first half of the year, ongoing softness in end-user demand has prompted Chinese manufacturers to engage in aggressive expansion, price reduction, and competition for orders, which inevitably impacts TSMC. There are even reports circulating about a potential loosening of 7nm production capacity.

In response, TSMC stated that its perspective and outlook on market demand align with the contents of its July press conference. As of now, no new updates are available. Furthermore, TSMC refrains from commenting on market speculations or shifts in customer business dynamics.

(Photo credit: TSMC)