As the demand for AI GPUs increases, TSMC’s advanced packaging capacity for CoWoS is struggling to keep up. Recently, according to a report from Commercial Times, NVIDIA has reportedly turned to Intel for advanced packaging solutions.

According to industry sources cited by the same report, TSMC’s CoWoS-S and Intel’s Foveros packaging technologies are similar, allowing clients to turn to Intel and secures the capacity needed quickly.

Despite its current struggling on transformation, Intel has been gradually developing its ‘s foundry services. In addition to clients like Qualcomm and Microsoft, Intel’s advanced packaging has also attracted interest from companies like Cisco and AWS.

Under the IDM 2.0 strategy, Intel has opened up its wafer outsourcing and foundry services to customers, establishing an the independent IFS foundry service. Earlier this year, Intel secured a major USD 15 billon foundry order from Microsoft for the first system-level AI foundry service, which is expected to use the Intel 18A process.

The report from Commercial Times further suggested that Microsoft’s move is anticipated to reduce its heavy reliance on TSMC. The report also indicates that chip customers, including NVIDIA, have engaged with Intel. Intel’s flexible foundry strategy, which can provide advanced packaging, software, and chiplet services tailored to customer needs, has been well-received by chipmakers.

Sources cited by the same report reveal that the U.S. has begun allocating specialized funds to increase investments in the advanced packaging sector as well. This move could highlight the importance of advanced packaging as the next key area for global competition in production capacity.

In November last year, the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST) released a report titled “National Advanced Packaging Manufacturing Program,” highlighting that advanced packaging technology is one of the key technologies in semiconductor manufacturing.

Additionally, the U.S. Department of Commerce plans to invest approximately USD 3 billion to advance the National Advanced Packaging Manufacturing Program. Intel, alongside Amkor, is another giant in local advanced packaging in the U.S.

The main focus of advanced packaging is on interconnect density, power efficiency, and scaling. From Foveros to hybrid bonding technology, Intel is gradually scaling down bumping pitch sizes, which allows for higher current loads and better thermal performance.

Furthermore, in May last year, Intel’s advanced packaging technology roadmap outlined plans to transition from traditional substrates to more advanced glass substrates.

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(Photo credit: Intel)

A previous report from Economic Daily News once reported that, Innolux is set to sell its 4th Plant in Tainan (5.5-generation LCD panel plant), which was closed in 2023. Moreover, the report has cited rumors in the market, claiming that both Micron and TSMC have been actively exploring the acquisition.

Eariler on August 1st, the latest report from MoneyDJ further suggests that TSMC is almost certain to secure the deal, primarily to expand its CoWoS capacity. Regarding this matter, neither company has commented on these market rumors.

On July 30, Innolux announced its plan to dispose of the TAC plant-related real estate at the Southern Taiwan Science Park (STSP) D section, so as to bolster operational funds. To expedite the process and meet business needs, the board authorized Chairman Jim Hung to negotiate terms and sign relevant contracts with potential buyers.

Reportedly, the sale price must not be lower than the asset’s book value in the most recent financial statements, taking into account professional valuation reports and market information.

The recent trend of FOPLP (Fan-Out Panel Level Packaging) is said to have fueled speculation and discussions about Innolux’s plant sale, leading to rumors that TSMC is on the verge of announcing the purchase.

Yet, per MoneyDJ, TSMC’s current FOPLP applications in the AI field primarily involve stacking on rectangular substrates, integrating them into 2.5D and 3D packages. Initially, TSMC prefers to complete the entire FOPLP process in-house, integrating the front-end and back-end technologies of the 3D fabric platform.

For Innolux, besides gaining considerable non-operating income, this opportunity also raises the prospect of future collaboration.

Notably, this rumored move comes as construction at TSMC’s first P1 plant in the Southern Taiwan Science Park’s Chiayi Campus was halted due to the discovery of potential archaeological remains.

With P1 construction paused, TSMC has prioritized the construction of the second plant (P2). However, current capacity is very tight, and the time required to complete and ramp up P2 to mass production may not meet customer demand. The long-term substantial demand has driven TSMC to seek additional suitable locations in advance.

It is indicated by MoneyDJ that though TSMC’s Chiayi plant is currently facing delays due to the archaeological site issue, Chiayi is still planned to be a major hub for CoWoS production in the long term, with six phases planned. Previously, the company had considered expanding SoIC (System on Integrated Chips) production in Yunlin, but has recently decided to put those plans on hold.

Overall, the latest industry estimates suggest that CoWoS monthly capacity could reach about 35,000 to 40,000 wafers this year. On 2025, if outsourcing to packaging and testing subcontractors is included, capacity could potentially exceed 60,000 wafers, or even more next year.

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(Photo credit: Innolux)

As TSMC stands at the core of the global semiconductor industry, NVIDIA founder Jensen Huang stirred up an AI frenzy when he visited Taiwan in June. According to a report from Commercial Times, during his visit, he met with TSMC founder Morris Chang and then-President C.C. Wei, and personally visited TSMC’s headquarters.

According to a report by Mirror Media on July 23rd, sources revealed that Huang requested TSMC to set up a dedicated CoWoS production line for NVIDIA at an external facility. However, this request was met with skepticism from TSMC’s senior management, resulting in a tense situation.

Notably, TSMC Chairman C.C. Wei recently pointed out that despite strong AI demand, the company has yet to achieve a supply-demand balance and continues to increase production capacity. Many customers are eager for advanced process capacity, and TSMC is striving to balance pricing and capacity. Wei also revealed that the profit margins for advanced packaging CoWoS are being adjusted to align more closely with the company’s average profit levels.

C.C. Wei emphasized TSMC’s commitment to meeting customer demands with three “Whatever” statements. Regarding timelines, he revealed that supply will remain tight through 2025, with hopes for improvement by 2026.

Sources cited by the report further estimates that current utilization rates for 5nm and 3nm processes are at full capacity. To address demand, production for 3nm is set to increase gradually from 100,000 wafers per month to approximately 125,000 wafers per month by the second half of the year.

The 2nm process is expected to start mass production in the fourth quarter of 2025, with a target monthly output of 30,000 wafers. With future expansion at the Kaohsiung plant, the combined monthly capacity of the Hsinchu Science Park and Kaohsiung facilities is projected to reach 120,000 to 130,000 wafers.

Despite escalating geopolitical risks, Wei stated that there will be no changes to TSMC’s expansion strategy, with projects in Arizona, Japan’s Kumamoto, and future European facilities proceeding as planned.

Currently, TSMC’s investment in its U.S. facilities has reached USD 65 billion. The Arizona site is expected to have three plants, with the first two set to start production in 2025 and 2028, focusing on 4/3nm and 3/2nm nodes, respectively.

TSMC’s advanced packaging plans in Taiwan include facilities in Hsinchu Science Park, Miaoli Zhunan, Taichung Central Taiwan Science Park, Tainan Southern Taiwan Science Park (taking over Longtan InFO), and Taoyuan Longtan (significantly expanding CoWoS). Construction is also scheduled to begin in 2024 at Miaoli Tongluo and Chiayi Science Park.

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(Photo credit: TSMC)

As TSMC and other major chip manufacturers compete for AI business opportunities, chip production capacity is unable to keep up with demand. Industry sources cited in a report from NIKKEI claimed that the slow expansion of high-end chip production capacity is due to different packaging and testing technologies used by various companies and calls for the industry to standardize as soon as possible.

Jim Hamajima, President of the Japan office of the Semiconductor Equipment and Materials International (SEMI), recently stated in an interview with NIKKEI that leading chip manufacturers like Intel and TSMC should adopt international standards for back-end processes to effectively and quickly increase production capacity.

Hamajima further noted that each company is trying to apply unique solutions in back-end processes, with TSMC and Intel using different technical standards, which leads to inefficiencies.

Semiconductor manufacturing is divided into two major parts: front-end and back-end processes. While the photolithography technology used in front-end processes widely adopts international standards set by SEMI, packaging and testing in back-end processes vary among manufacturers. For example, TSMC uses CoWoS technology for advanced packaging, while Samsung Electronics uses I-Cube technology.

In recent years, chip manufacturers have actively invested in the development of advanced packaging technologies, primarily because front-end processes face technical bottlenecks, making back-end processes the key to gaining a competitive edge.

Hamajima believes that the current state of back-end processes in the semiconductor industry is “Balkanized,” with each company adhering to its own technologies, leading to a fragmented industry. He warns that this issue will start to impact profit margins as more powerful chips are produced in the future.

Hamajima stated that if semiconductor manufacturers adopt standardized automated production technologies and material specifications, it will be easier to acquire manufacturing equipment and upstream material supplies when expanding production capacity.

Hamajima is a director of a recently launched consortium led by Intel and 14 Japanese companies to jointly develop automated systems for back-end processes. The collaborating companies include Japanese companies such as Omron, Yamaha Motor, Resonac, and Shin-Etsu Polymer, a subsidiary of Shin-Etsu Chemical Industry.

Hamajima noted that Japan, with its numerous automation equipment and semiconductor material suppliers, is an ideal location to test international standards for back-end processes.

He also acknowledged that currently, Intel is the only multinational chip manufacturer in the alliance, which might lead to the development of technical standards that favor Intel. However, he emphasized that the alliance welcomes other chip manufacturers to join, and the research outcomes will serve as a reference for future industry standard-setting.

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(Photo credit: TSMC)

TSMC continues to showcase its drive in the advanced packaging market. According to a report from MoneyDJ, TSMC has forecasted that CoWoS will remain in high demand through 2025, with potential for capacity to double in two consecutive years. TSMC is also entering the FOPLP (Fan-Out Panel-Level Packaging) space, a technology that OSATs and panel manufacturers have been developing for years, with a goal to launch it in three years.

TSMC’s stronghold on advanced packaging technologies has raised market concerns that OSATs may see their opportunities diminished as TSMC consolidates its market position.

During its earnings call, TSMC introduced “Foundry 2.0,” a new definition for the semiconductor manufacturing industry. This expanded definition now includes not only foundry services but also packaging, testing, photomask production, and other integrated component manufacturing, excluding memory production. TSMC further stated that this new definition will better reflect the company’s growing market opportunities and that the company will focus solely on cutting-edge back-end technologies.

Under this new definition, TSMC estimates the Foundry 2.0 industry will be nearly USD 250 billion in 2023, up from the previous estimate of USD 115 billion. With this new scope, the industry is expected to grow by 10% annually in 2024. Additionally, TSMC’s market share in Foundry 2.0 (logic semiconductor manufacturing) for 2023 is revised to 28%, with expectations for continued growth in 2024.

The sources cited by the report has pointed out that, observing TSMC’s process advancements, the 3nm process began mass production in 2022, with the 2nm process set for 2025, indicating a lengthening of the development cycle to three years.

Regarding the aforementioned nodes, advanced packaging may help enhance performance, reduce costs, and has the advantage of binding high-end products from top-tier clients. Additionally, the investment required for advanced packaging is significantly smaller compared to frontend technologies, making it a crucial area of focus.

The report continues to note that TSMC currently retains the majority of major CoWoS orders and collaborates with OSATs in the WoS segment. However, TSMC has reportedly yet finalized its CoW segment outsourcing orders.

Meanwhile, AMD and NVIDIA have reportedly turned to Amkor and ASE’s subsidiary, Siliconware, for CoWoS-related products, focusing on cost-sensitive high-performance products. Amkor is expected to supply about 70,000 to 80,000 units annually this year, while Siliconware can provide about 50,000 to 60,000 units.

Additionally, OSATs have been confined to mature IC FOPLP technologies for the past 7-8 years, whereas TSMC has announced it will launch its own FOPLP technology in three years.

TSMC’s planned FOPLP is a rectangular CoWoS-L concept, offering advantages in low unit cost and large-size packaging. However, it faces physical limitations such as issues in coating, spinning, and warping. TSMC, backed by a substantial equipment and materials supply chain, is well-positioned to address these challenges.

As for opportunities for other OSATs, the advanced packaging market is actually vast and can be broadly categorized into flip-chip, fan-out, fan-in, 2.5D/3D, and embedded die packaging.

These technologies can be integrated, and OSATs are not limited to TSMC’s top-tier Info, CoWoS, or SoIC technologies. OSATs can offer more cost-effective advanced packaging solutions compared to fabs, providing competitive alternatives in terms of cost and performance.

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(Photo credit: TSMC)